SAA7108AE Datasheet, PDF (62/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
CVBS input
expansion port
data output
burst
processing delay ADC to expansion port:
140 × 1/LLC
sync clipped
HREF (50 Hz)
CREF
720 × 2/LLC
50 Hz
CREF2
HS (50 Hz)
5 × 2/LLC
programming range 108
0
(step size: 8/LLC)
12 × 2/LLC
144 × 2/LLC
2 × 2/LLC
−107
HREF (60 Hz)
60 Hz
CREF
CREF2
HS (60 Hz)
720 × 2/LLC
1 × 2/LLC
16 × 2/LLC
138 × 2/LLC
2 × 2/LLC
programming range ₁₀₇
0
(step size: 8/LLC)
−106
mhb542
The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see
Table 160 and Table 161); their polarity can be inverted via RTP0 and/or RTP1.
The signals HREF and HS are available on pin XRH (see Table 162).
Fig 35. Horizontal timing diagram (50/60 Hz)
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
62 of 208