SAA7108AE Datasheet, PDF (81/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Additionally the output formatter limits the amplitude range of the video data (controlled by
ILLV[85h[5]]); see Table 31.
Table 29. Byte stream for different output formats
Output format Byte sequence for 8-bit output modes
Y-C_B-C_R 4 : 2 : 2 C_B0 Y0 C_R0 Y1 C_B2 Y2 C_R2 Y3 C_B4 Y4 C_R4 Y5 C_B6 Y6
Y-C_B-C_R 4 : 1 : 1 C_B0 Y0 C_R0 Y1 C_B4 Y2 C_R4 Y3 Y4 Y5 Y6 Y7 C_B8 Y8
Y only
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13
Table 30.
Name
C_Bn
Yn
C_Rn
Explanation to Table 29
Explanation
C_B (B − Y) color difference component, pixel number n = 0, 2, 4 to 718
Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719
C_R (R − Y) color difference component, pixel number n = 0, 2, 4 to 718
Table 31. Limiting range on I port
Limit step Valid range
Suppressed codes (hexadecimal value)
ILLV[85h[5]] _{Decimal value Hexadecimal value Lower range}
Upper range
0
1 to 254
01 to FE
00
FF
1
8 to 247
08 to F7
00 to 07
F8 to FF
9.5.2 Video FIFO (subaddress 86h)
The video FIFO at the scaler output contains 32 double words. That corresponds to
64 pixels in 16-bit Y-C_B-C_R 4 : 2 : 2 format. But as the entire scaler can act as a pipeline
buffer, the actual available buffer capacity for the image port is much higher, and can
exceed beyond a video line.
The image port and the video FIFO, can operate with the video source clock (synchronous
mode) or with an externally provided clock (asynchronous and burst mode), as
appropriate for the VGA controller or attached frame buffer.
The video FIFO provides 4 internal flags, reporting to what extent the FIFO is actually
filled.
These are:
• The FIFO Almost Empty (FAE) flag
• The FIFO Combined Flag (FCF) or FIFO filled, which is set at almost full level and
reset, with hysteresis, only after the level crosses below the almost empty mark
• The FIFO Almost Full (FAF) flag
• The FIFO Overflow (FOVL) flag
The trigger levels for FAE and FAF are programmable by FFL[1:0] 86h[3:2] (16, 24, 28,
full) and FEL[1:0] 86h[1:0] (16, 8, 4, empty).
The state of this flag can be seen on pins IGP0 or IGP1. The pin mapping is defined by
subaddresses 84h and 85h; see Section 10.5.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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