SAA7108AE Datasheet, PDF (125/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
SAA7108AE_SAA7109AE_3
Product data sheet
Table 116. Subaddress D2h
Data byte Description
HLPA
RAM start address for the HD sync line pattern array; the byte following
subaddress D2 points to the first cell to be loaded with the next transmitted byte;
succeeding cells are loaded by auto-incrementing until stop condition. Each line
pattern array entry consists of 4 value-duration pairs occupying 2 bytes; see
Table 117. The array has 7 entries.
HPD
HD pattern duration. The value defines the time in pixel clocks (HPD + 1) the
corresponding value HPV is added to the HD output signal. If 0, this entry will be
skipped.
HPV
HD pattern value pointer. This gives the index in the HD value array containing the
level to be inserted into the HD output path. If the MSB of HPV is logic 1, the value
will only be inserted into the Y/GREEN channel of the HD data path, the other
channels remain unchanged.
Table 117. Layout of the data bytes in the line pattern array
Byte
Description
0
HPD07 HPD06 HPD05 HPD04 HPD03
1
HPV03 HPV02 HPV01 HPV00 0
2
HPD17 HPD16 HPD14 HPD14 HPD13
3
HPV13 HPV12 HPV11 HPV10 0
4
HPD27 HPD26 HPD25 HPD24 HPD23
5
HPV23 HPV22 HPV21 HPV20 0
6
HPD37 HPD36 HPD35 HPD34 HPD33
7
HPV33 HPV32 HPV31 HPV30 0
HPD02
0
HPD12
0
HPD22
0
HPD32
0
HPD01
HPD09
HPD11
HPD19
HPD21
HPD29
HPD31
HPD39
HPD00
HPD08
HPD10
HPD18
HPD20
HPD28
HPD30
HPD38
Table 118. Subaddress D3h
Data byte Description
HPVA
RAM start address for the HD sync value array; the byte following subaddress D3
points to the first cell to be loaded with the next transmitted byte; succeeding cells
are loaded by auto-incrementing until stop condition. Each line pattern array entry
consists of 2 bytes. The array has 8 entries.
HPVE
HD pattern value entry. The HD path will insert a level of (HPV + 52) × 0.66 IRE into
the data path. The value is signed 8-bits wide; see Table 119.
HHS
HD horizontal sync. If the HD engine is active, this value will be provided at
pin HSM_CSYNC; see Table 119.
HVS
HD vertical sync. If the HD engine is active, this value will be provided at pin VSM;
see Table 119.
Table 119. Layout of the data bytes in the value array
Byte
Description
0
HPVE7 HPVE6 HPVE5 HPVE4 HPVE3
1
0
0
0
0
0
HPVE2
0
HPVE1
HVS
HPVE0
HHS
Table 120. HD sync trigger state 1 register, subaddress D4h, bit description
Bit Symbol Description
7 to 0 HLCT[7:0] with HLCT[9:8] (see Table 121) state of the HD line counter after trigger
(counts backwards)
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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