SAA7108AE Datasheet, PDF (174/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 232. Decoder part start setup values for the three main standards …continued
Subaddress Register function
(hexadecimal)
Bit name^[1]
Values (hexadecimal)
NTSC M PAL B, D, SECAM
G, H and I
0F
chrominance gain control
ACGC and CGAIN6 to CGAIN0
2A
2A
80
10
chrominance control 2
OFFU1, OFFU0, OFFV1, OFFV0, 0E
06
00
CHBW and LCBW2 to LCBW0
11
mode/delay control
COLO, RTP1, HDEL1, HDEL0,
00
00
00
RTP0 and YDEL2 to YDEL0
12
RT signal control
RTSE13 to RTSE10 and
RTSE03 to RTSE00
00
00
00
13
RT/X port output control
RTCE, XRHS, XRVS1, XRVS0,
00
00
00
HLSEL and OFTS2 to OFTS0
14
analog/ADC/compatibility
CM99, UPTCV, AOSL1, AOSL0, 00
00
00
control
XTOUTE, OLDSB,
APCK1 and APCK0
15
VGATE start, FID change
VSTA7 to VSTA0
11
11
11
16
VGATE stop
VSTO7 to VSTO0
FE
FE
FE
17
miscellaneous, VGATE
LLCE, LLC2E, X, X, X, VGPS,
40
40
40
configuration and MSBs
VSTO8 and VSTA8
18
raw data gain control
RAWG7 to RAWG0
40
40
40
19
raw data offset control
RAWO7 to RAWO0
80
80
80
1A to 1E
reserved
X, X, X, X, X, X, X, X
00
00
00
1F
status byte video decoder
INTL, HLVLN, FIDT, GLIMT, GLIMB, read only
(OLDSB = 0)
WIPA, COPRO and RDCAP
[1] All X values must be set to logic 0.
12.2 Audio clock generation part
The given values force the following behavior of the SAA7108AE; SAA7109AE audio
clock generation part:
• Used crystal is 24.576 MHz
• Expected field frequency is 59.94 Hz (e.g. NTSC M standard)
• Generated audio master clock frequency at pin AMCLK is
256 kHz × 44.1 kHz = 11.2896 MHz
• AMCLK is externally connected to AMXCLK (short-cut between pins K12 and J12)
• ASCLK = 32 kHz × 44.1 kHz = 1.4112 MHz
• ALRCLK is 44.1 kHz
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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