SAA7108AE Datasheet, PDF (85/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 34. Bytes stream of the data slicer
Nick Comment
name
Bit 7
Bit 6
DID,
SAV,
EAV
subaddress 5Dh = 00h
subaddress 5Dh bit 5 = 1
subaddress 5Dh
bit 5 = 3Eh^[5]
NEP^[1]
NEP^[1]
1
EP^[2]
EP^[2]
FID^[3]
subaddress 5Dh
bit 5 = 3Fh^[5]
0
FID^[3]
SDID programmable via
subaddress 5Eh
NEP^[1] EP^[2]
DC^[8]
NEP^[1] EP^[2]
IDI1
OP^[9]
FID^[3]
IDI2
OP^[9]
LN2^[10]
CS check sum byte
CS6
CS6
BC valid byte count
OP^[9]
0
Bit 5
0
0
V^[6]
V^[6]
D5[5Eh]
DC5
LN8^[10]
LN1^[10]
CS5
CNT5
Bit 4
1
D4[5Dh]
H^[7]
H^[7]
D4[5Eh]
DC4
LN7^[10]
LN0^[10]
CS4
CNT4
Bit 3
0
D3[5Dh]
P3
P3
D3[5Eh]
DC3
LN6^[10]
DT3^[11]
CS3
CNT3
Bit 2
FID^[3]
D2[5Dh]
P2
P2
D2[5Eh]
DC2
LN5^[10]
DT2^[11]
CS2
CNT2
Bit 1
I1^[4]
D1[5Dh]
P1
P1
D1[5Eh]
DC1
LN4^[10]
DT1^[11]
CS1
CNT1
Bit 0
I0^[4]
D0[5Dh]
P0
P0
D0[5Eh]
DC0
LN3^[10]
DT0^[11]
CS0
CNT0
[1] NEP = inverted EP; see Table note 2.
[2] EP = even parity of bits 5 to 0.
[3] FID = 0: field 1; FID = 1: field 2.
[4] I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field.
[5] Subaddress 5Dh at 3Eh and 3Fh are used for ITU 656 like SAV/EAV header generation; recommended value.
[6] V = 0: active video; V = 1: blanking.
[7] H = 0: start of line; H = 1: end of line.
[8] DC = data count in double words according to the data type.
[9] OP = odd parity of bits 6 to 0.
[10] LN = line number.
[11] DT = data type according to Table 28.
9.6 Audio clock generation (subaddresses 30h to 3Fh)
The SAA7108AE; SAA7109AE incorporates the generation of a field-locked audio clock
as an auxiliary function for video capture. An audio sample clock, that is locked to the field
frequency, ensures that there is always the same predefined number of audio samples
associated with a field, or a set of fields. This ensures synchronous playback of audio and
video after digital recording (e.g. capture to hard disk), MPEG or other compression, or
non-linear editing.
9.6.1 Master audio clock
The audio clock is synthesized from the same crystal frequency as the line-locked video
clock is generated. The master audio clock is defined by the parameters:
• Audio master Clocks Per Field, ACPF[17:0] 32h[1:0] 31h[7:0] 30h[7:0] according to
the equation: ACPF[17:0] = round_^a--_f--^ui--_e-^d--_l--^id--^o-----_f-^f-_r-^r-_e-^e---_q-^q--_u-^u--_e-^e--_n-ⁿ---_c-^c--_y-^y-_
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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