SAA7108AE Datasheet, PDF (87/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 36. Programming examples for ASCLK/ALRCLK clock generation
AMXCLK
(MHz)
ASCLK
(kHz)
SDIV
Decimal Hex
ALRCLK LRDIV
(kHz)
Decimal Hex
12.288
1 536
3
03
48
16
10
768
7
07
48
8
08
11.2896
1 411.2
3
03
44.1
16
10
2 822.4
1
01
44.1
32
10
8.192
1 024
3
03
32
16
10
2 048
1
01
32
32
10
9.6.3 Other control signals
Further control signals are available to define reference clock edges and vertical
references; see Table 37.
Table 37. Control signals
Control signal Description
APLL[3Ah[3]] Audio PLL mode
0 = PLL closed
1 = PLL open
AMVR[3Ah[2]] Audio Master clock Vertical Reference
0 = internal vertical reference
1 = external vertical reference
LRPH[3Ah[1]] ALRCLK phase
0 = invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1 = do not invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
SCPH[3Ah[0]] ASCLK phase
0 = invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1 = do not invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK
10. Input/output interfaces and ports of digital video decoder part
The SAA7108AE; SAA7109AE has 5 different I/O interfaces:
• Analog video input interface, for analog CVBS and/or Y and C input signals
• Audio clock port
• Digital real-time signal port (RT port)
• Digital video expansion port (X port), for unscaled digital video input and output
• Digital image port (I port) for scaled video data output and programming
• Digital host port (H port) for extension of the image port or expansion port from
8-bit to 16-bit
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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