SAA7108AE Datasheet, PDF (78/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 26. Examples for vertical phase offset usage: global equations
Input field under Output field
processing
interpretation
Used
Equation for phase offset
abbreviation calculation (decimal values)
Upper input lines upper output lines UP-UP
PHO + 16
Upper input lines lower output lines UP-LO
PHO + -^Y---^S----^C----^Y-₆---^[₄--¹---⁵----^:--⁰---^]- + 16
Lower input lines upper output lines LO-UP
PHO
Lower input lines lower output lines LO-LO
PHO + ^Y----^S----^C----^Y-₆---^[₄--¹---⁵----^:--⁰---^]-
Table 27. Vertical phase offset usage; assignment of the phase offsets
Detected input
field ID
Task
status
bit
Vertical phase Case
offset
Equation to be used
0 = upper lines 0
YPY0[7:0] and case 1^[1]
YPC0[7:0]
case 2^[2]
UP-UP (PHO)
UP-UP
case 3^[3] UP-LO
0 = upper lines 1
YPY1[7:0] and case 1
YPC1[7:0]
case 2
UP-UP (PHO)
UP-LO
case 3
UP-UP
1 = lower lines 0
YPY2[7:0] and case 1
YPC2[7:0]
LO-LO


PHO
+
Y_----S_----C_----Y_-6---[_4--1_---5_----:_--0_---]_-
–
16_
1 = lower lines 1
YPY3[7:0] and
YPC3[7:0]
case 2
case 3
case 1
LO-UP
LO-LO
LO-LO


PHO
+
-^Y---^S----^C----^Y-₆---^[₄--¹---⁵----^:--⁰---^]-
–
16_
case 2
case 3
LO-LO
LO-UP
[1] Case 1: OFIDC[90h[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0
as upper output lines.
[2] Case 2: OFIDC[90h[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as
upper output lines.
[3] Case 3: OFIDC[90h[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as
upper output lines.
9.4 VBI data decoder and capture (subaddresses 40h to 7Fh)
The SAA7108AE; SAA7109AE contains a versatile VBI data decoder.
The implementation and programming model is in accordance with the VBI data slicer
built into the multimedia video data acquisition circuit SAA5284.
The circuitry recovers the actual clock phase during the clock run-in period, slices the data
bits with the selected data rate, and groups them into bytes. The result is buffered into a
dedicated VBI data FIFO with a capacity of 2 × 56 bytes (2 × 14 double words). The clock
frequency, signal source, field frequency and accepted error count must be defined in
subaddress 40h.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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