SAA7108AE Datasheet, PDF (12/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 4.
Symbol
PD10
Pin description …continued
Pin
Type^[1]
C2
I
TTX_SRES
C3
I
TTXRQ_XCLKO2 C4
O
V_SSIe
C5
S
BLUE_CB_CVBS C6
O
GREEN_VBS_CVBS C7
O
RED_CR_C_CVBS C8
O
V_DDAe
TEST2
C9
S
C10
I
HPD2
C11
I/O
HPD5
C12
I/O
IPD1
C13
O
IPD5
C14
O
TDOe
D1
O
RESe
D2
I
TMSe
D3
I/pu
V_DDIEe
V_SSIe
V_DDXe
VSM
D4
S
D5
S
D6
S
D7
O
HSM_CSYNC
D8
O
V_DDAe
V_DDEd
V_DDId
HPD6
IPD2
IPD6
TCKe
SCLe
HSVGC
D9
S
D10
S
D11
S
D12
I/O
D13
O
D14
O
E1
I/pu
E2
I(/O)
E3
I/O
V_SSEe
V_SSId
n.c.
IPD3
IPD7
VSVGC
PIXCLKI
E4
S
E11
S
E12
-
E13
O
E14
O
F1
I/O
F2
I
Description
see Table 12, Table 17 and Table 18 for pin assignment with different encoder
input formats
teletext input or sync reset input (encoder)
teletext request output or 13.5 MHz clock output of the crystal oscillator
(encoder)
digital ground core (encoder)
BLUE or C_B or CVBS output
GREEN or VBS or CVBS output
RED or C_R or C or CVBS output
3.3 V analog supply voltage (encoder)
scan test input 2; do not connect
MSB − 5 of HPD output bus
MSB − 2 of HPD output bus
MSB − 6 of IPD output bus
MSB − 2 of IPD output bus
test data output for BST (encoder)^[4]
reset input (encoder); active LOW
test mode select input for BST (encoder)^[4]
3.3 V digital supply voltage for core and peripheral cells (encoder)
digital ground core (encoder)
3.3 V supply voltage for oscillator (encoder)
vertical synchronization output to VGA monitor (non-interlaced)
horizontal synchronization output to VGA monitor (non-interlaced) or composite
sync for RGB-SCART
3.3 V analog supply voltage (encoder)
3.3 V digital supply voltage for peripheral cells (decoder)
3.3 V digital supply voltage for core (decoder)
MSB − 1 of HPD output bus
MSB − 5 of IPD output bus
MSB − 1 of IPD output bus
test clock input for BST (encoder)^[4]
serial clock input (I²C-bus encoder) with inactive output path
horizontal synchronization output to Video Graphics Controller (VGC) (optional
input)
digital ground peripheral cells (encoder)
digital ground core (decoder)
not connected
MSB − 4 of IPD output bus
MSB of IPD output bus
vertical synchronization output to VGC (optional input)
pixel clock input (looped through)
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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