SAA7108AE Datasheet, PDF (45/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
• Loop filter chrominance PLL (only active for PAL/NTSC standards)
• PAL/SECAM sequence detection, H/2-switch generation
The increment generation circuit produces the Discrete Time Oscillator (DTO) increment
for both subcarrier generation blocks. It contains a division by the increment of the
line-locked clock generator to create a stable phase-locked sine signal under all conditions
(e.g. for non-standard signals).
The PAL delay line block eliminates crosstalk between the chrominance channels in
accordance with the PAL standard requirements. For NTSC color standards the delay line
can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1.
It is always disabled during VBI or raw data lines programmable by the LCRn registers
(subaddresses 41h to 57h); see Section 9.2. The embedded line delay is also used for
SECAM recombination (cross-over switches).
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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