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| SAA7108AE Datasheet, PDF (56/208 Pages) NXP Semiconductors – HD-CODEC | |||
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NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 19. Decoder clock frequencies
Clock
XTALO
LLC
LLC2
LLC4 (internal)
LLC8 (virtual)
Frequency (MHz)
24.576 or 32.110
27
13.5
6.75
3.375
LFCO
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
OSCILLATOR
LLC
DIVIDER
1/2
Fig 29. Block diagram of the clock generation circuit
DIVIDER
1/2
mhb330
LLC2
9.1.6 Power-on reset and CE input
A missing clock, insufï¬cient digital or analog VDDAd supply voltages (below 2.7 V) will start
the reset sequence; all outputs are forced to 3-state (see Figure 30). The indicator output
RESd is LOW for approximately 128 LLC after the internal reset and can be applied to
reset other circuits of the digital TV system.
It is possible to force a reset by pulling the CE input to ground. After the rising edge of CE
and sufï¬cient power supply voltage, the outputs LLC, LLC2 and SDAd return from 3-state
to active, while the other signals have to be activated via programming.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 â 6 February 2007
© NXP B.V. 2007. All rights reserved.
56 of 208
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