SAA7108AE Datasheet, PDF (76/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
9.3.3.3 Use of the vertical phase offsets
As described in Section 9.3.1.3, the scaler processing may run randomly over the
interlaced input sequence. Additionally the interpretation and timing between ITU 656 field
ID and real-time detection by means of the state of H-sync at the falling edge of V-sync
may result in different field ID interpretation.
A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the
interlaced input fields are processed, without regard to the actual scale at the starting
point of operation (see Figure 40).
Four events should be considered, they are illustrated in Figure 41.
In Table 26 and Table 27 PHO is a usable common phase offset.
It should be noted that the equations of Figure 41 produce an interpolated output, also for
the unscaled case, as the geometrical reference position for all conversions is the position
of the first line of the lower field; see Table 26.
If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference
for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the ¹â„₂ line
phase shift (PHO + 16) that can be skipped. This case is listed in Table 27.
The SAA7108AE; SAA7109AE supports 4 phase offset registers per task and component
(luminance and chrominance). The value of 20h represents a phase shift of one line.
The registers are assigned to the following events; e.g. subaddresses B8h to BBh:
• B8h: 00 = input field ID 0, task status bit 0 (toggle status; see Section 9.3.1.3)
• B9h: 01 = input field ID 0, task status bit 1
• BAh: 10 = input field ID 1, task status bit 0
• BBh: 11 = input field ID 1, task status bit 1
Depending on the input signal (interlaced or non-interlaced) and the task processing
50 Hz or field reduced processing with one or two tasks (see examples in
Section 9.3.1.3), other combinations may also be possible, but the basic equations are the
same.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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