|
SAA7108AE Datasheet, PDF (73/208 Pages) NXP Semiconductors – HD-CODEC | |||
|
◁ |
NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 25. Example of XACL[5:0] usage
Prescale
ratio
XPSC Recommended values
[5:0] For lower bandwidth requirements
XACL[5:0] XC2_1
XDCG[2:0]
1
1
0
0
0
1â2
2
2
1
2
(1 2 1) Ã 1â4[1]
1â3
3
4
1
3
(1 2 2 2 1) Ã 1â8[1]
1â4
4
7
0
3
(1 1 1 1 1 1 1 1) Ã 1â8[1]
1â5
5
8
1
4
(1 2 2 2 2 2 2 2 1) Ã 1â16[1]
1â6
6
8
1
4
(1 2 2 2 2 2 2 2 1) Ã 1â16[1]
1â7
7
8
1
4
(1 2 2 2 2 2 2 2 1) Ã 1â16[1]
1â8
8
15
0
4
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) Ã 1â16[1]
1â9
9
15
0
4
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) Ã 1â16[1]
1â10
10
16
1
5
(1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1) Ã 1â32[1]
1â13
13
16
1
5
1â15
15
31
0
5
1â16
16
31
0
5
1â19
19
32
1
6
1â31
31
32
1
6
1â32
32
63
1
7
1â35
35
63
1
7
For higher bandwidth requirements
XACL[5:0] XC2_1
XDCG[2:0]
FIR preï¬lter
PFY[1:0]/
PFUV[1:0]
0
0
0
0 to 2
1
0
1
0 to 2
(1 1) Ã 1â2[1]
3
0
2
2
(1 1 1 1) Ã 1â4[1]
4
1
3
2
(1 2 2 2 1) Ã 1â8[1]
7
0
3
2
(1 1 1 1 1 1 1 1) Ã 1â8[1]
7
0
3
3
(1 1 1 1 1 1 1 1) Ã 1â8[1]
7
0
3
3
(1 1 1 1 1 1 1 1) Ã 1â8[1]
8
1
4
3
(1 2 2 2 2 2 2 2 1) Ã 1â16[1]
8
1
4
3
(1 2 2 2 2 2 2 2 1) Ã 1â16[1]
8
1
4
3
(1 2 2 2 2 2 2 2 1) Ã 1â16[1]
16
1
5
3
16
1
5
3
16
1
5
3
32
1
6
3
32
1
6
3
32
1
6
3
63
1
7
3
[1] Resulting FIR function.
9.3.2.2
Horizontal ï¬ne scaling (variable phase delay ï¬lter; subaddresses A8h to AFh and
D8h to DFh)
The horizontal ï¬ne scaling (VPD) should operate at scaling ratios between 1â2 and 2
(0.8 and 1.6), but can also be used for direct scaling in the range from 1â7.999 to
(theoretical) zoom 3.5 (restriction due to the internal data path architecture), without
prescaler.
In combination with the prescaler a compromise between sharpness impression and alias
can be found. This is signal source and application dependent.
For the luminance channel a ï¬lter structure with 10 taps is implemented, for the
chrominance a ï¬lter with 4 taps.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 â 6 February 2007
© NXP B.V. 2007. All rights reserved.
73 of 208
|
▷ |