SAA7108AE Datasheet, PDF (7/208 Pages) NXP Semiconductors – HD-CODEC

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RESd
CE
XTOUTd
XTALId
XTALOd
AI11
AI12
AI21
AI22
AI23
AI24
AOUT
AI1D
AI2D
AGND
LLC2 RTS0 XCLK XPD[7:0]
XRV XTRI
TEST5 TEST3 TEST1
LLC RTCO RTS1 XDQ
(1)
XRH XRDY
M14 L14 L13 K13 L10 M3 M4 K2, K3,
N2 L5 N3 K1
L1 to L3,
M1, M2, N1
REAL-TIME OUTPUT EXPANSION PORT PIN MAPPING
HPD [7:0]
SDAd SCLd
A13, D12, C12, L12 M11
B12, A12, C11,
B11, A11
I/O CONTROL
I²C-BUS
TEST4 TEST2 TEST0
J2 J1 J3 C10 B10 H13
M12
N14
P4
CLOCK GENERATION
AND
P2
POWER-ON CONTROL
P3
P13
X PORT I/O FORMATTING
chrominance of 16-bit input
PROGRAMMING
REGISTER
ARRAY
A/B
REGISTER
MUX
SAA7108AE
SAA7109AE
P11
P10
P9
ANALOG
DUAL
P7
ADC
P6
M10
DIGITAL
DECODER
WITH
ADAPTIVE
COMB
FILTER
P12
P8
BOUNDARY
AUDIO
SCAN
CLOCK
N10
TEST
GENERATION
EVENT CONTROLLER
FIR-PREFILTER
PRESCALER
AND
SCALER BCS
LINE
FIFO
BUFFER
VERTICAL
SCALING
HORIZONTAL
FINE
(PHASE)
SCALING
GENERAL PURPOSE
VBI DATA SLICER
VIDEO
FIFO
TEXT
FIFO
32
to
8 (16)
MUX
E14, D14,
C14, B14,
E13, D13,
C13, B13
H14
G12
F13
F14
G13
H12
J14
D11, F11,
M7,
J4, J11, D10, G11, M8, M9, E11, K4, H4, H11, N7 to N9,
N4 M6 M5 N6 N5 K12 J13 K14 J12 L8 P5 L4, L11 L7, L9 N11 K11
L6, M13 N12, N13
VIDEO / TEXT
ARBITER
TCKd TDId AMCLK ASCLK VDDXd V_DDId
TRSTd TMSd TDOd ALRCLK AMXCLK V_SSXd
(1)
V_DDEd
V_DDAd
V_SSId
V_SSEd
V_SSAd
G14
mbl791
IPD [7:0]
IDQ
IGPH
IGPV
IGP0
IGP1
ICLK
ITRDY
ITRI
(1) The pins RTCO and ALRCLK are used for configuration of the I²C-bus interface and the definition of the crystal oscillator frequency at RESET (pin strapping).
Fig 3. Block diagram (video decoder part)