SAA7108AE Datasheet, PDF (107/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 54. Wide screen signal registers, subaddresses 26h and 27h, bit description
Legend: * = default value after reset.
Subaddress Bit Symbol Access Value Description
27h
7
WSSON R/W 0* wide screen signalling output is disabled
1
wide screen signalling output is enabled
6
-
R/W 0
must be programmed with logic 0 to ensure
compatibility to future enhancements
5 to 3 WSS[13:11] R/W -
wide screen signalling bits, reserved
2 to 0 WSS[10:8] R/W -
wide screen signalling bits, subtitles
26h
7 to 4 WSS[7:4] R/W -
wide screen signalling bits, enhanced
services
3 to 0 WSS[3:0] R/W -
wide screen signalling bits, aspect ratio
Table 55. Real-time control and burst start register, subaddress 28h, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7 and 6 -
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
5 to 0 BS[5:0] R/W
starting point of burst in clock cycles
21h* PAL: BS = 33; strapping pin FSVGC tied to HIGH
19h* NTSC: BS = 25; strapping pin FSVGC tied to LOW
Table 56. Sync reset enable and burst end register, subaddress 29h, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7
SRES R/W 0* pin TTX_SRES accepts a teletext bit stream (TTX)
1
pin TTX_SRES accepts a sync reset input (SRES); a HIGH
impulse resets synchronization of the encoder (first field, first
line)
6
-
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
5 to 0 BE[5:0] R/W
ending point of burst in clock cycles
1Dh* PAL: BE = 29; strapping pin FSVGC tied to HIGH
1Dh* NTSC: BE = 29; strapping pin FSVGC tied to LOW
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
107 of 208