SAA7108AE Datasheet, PDF (94/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the
scalers acquisition window are defined by XDV[1:0] 92h[5:4] and XDH[92h[2]]. The signal
polarity of the qualifier can also be defined (bit XDQ[92h[1]]). Alternatively to a qualifier,
the input clock can be applied to a gated clock (clock gated with a data qualifier, controlled
by bit XCKS[92h[0]]). In this event, all input data will be qualified.
10.5 Image port (I port)
The image port transfers data from the scaler as well as from the VBI data slicer, if
selected (maximum 33 MHz). The reference clock is available at the ICLK pin, as an
output or as an input (maximum 33 MHz). As output, ICLK is derived from the line-locked
decoder or expansion port input clock. The data stream from the scaler output is normally
discontinuous. Therefore valid data during a clock cycle is accompanied by a data
qualifying (data valid) flag on pin IDQ. For pin constrained applications the IDQ pin can be
programmed to function as a gated clock output (bit ICKS2[80h[2]]).
The data formats at the image port are defined in double words of 32 bits (4 bytes), such
as the related FIFO structures. However, the physical data stream at the image port is
only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for
chrominance data. The four bytes of the double words are serialized in words or bytes.
Available formats are as follows:
• Y-C_B-C_R 4 : 2 : 2
• Y-C_B-C_R 4 : 1 : 1
• Raw samples
• Decoded VBI data
For handshake with the receiving VGA controller, or other memory or bus interface
circuitry, F, H and V reference signals and programmable FIFO flags are provided. The
information is provided on pins IGP0, IGP1, IGPH and IGPV. The functionality on these
pins is controlled via subaddresses 84h and 85h.
VBI data is collected over an entire line in its own FIFO and transferred as an
uninterrupted block of bytes. Decoded VBI data can be signed by the VBI flag on pin IGP0
or IGP1.
As scaled video data and decoded VBI data may come from different and asynchronous
sources, an arbitration scheme is needed. Normally the VBI data slicer has priority.
The image port consists of the pins and/or signals, as listed in Table 46.
For pin constrained applications, or interfaces, the relevant timing and data reference
signals can also be encoded into the data stream. Therefore the corresponding pins do
not need to be connected. The minimum image port configuration requires 9 pins only, i.e.
8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are
defined in close relationship to the ITU-R BT.656 (D1) recommendation, where possible.
The following deviations from “ITU 656 recommendation” are implemented at the
SAA7108AE; SAA7109AEs image port interface:
• SAV and EAV codes are only present in those lines, where data is to be transferred,
i.e. active video lines, or VBI raw samples, no codes for empty lines
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
94 of 208