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SAA7108AE Datasheet, PDF (84/208 Pages) NXP Semiconductors – HD-CODEC
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invalid data
or
end of raw VBI line
timing reference code internal header
sliced data
and filling data
timing reference code invalid data
...
00 00 FF 00 00 SAV SDID DC IDI1 IDI2 D1_3 D1_4 D2_1
... DDC_3 DDC_4 CS BC FF 00 00 EAV 00 00 ...
... FF 00 00 EAV
ANC header
D1_1 D1_2
internal header
sliced data
ANC data output is only filled up
to the Dword boundary
mhb549
00 FF FF DID SDID DC IDI1 IDI2 D1_3 D1_4 ... DDC_3 DDC_4 CS BC 00 00 ...
ANC header active for DID (subaddress 5Dh) < 3Eh
Fig 42. Sliced data formats on the I port in 8-bit mode
Table 33.
Name
SAV
SDID
DC
IDI1
IDI2
Dn_m
DDC_4
CS
BC
EAV
Explanation to Figure 42
Explanation
start of active data; see Table 34
sliced data identification: NEP[1], EP[2], SDID5 to SDID0, freely programmable via I2C-bus subaddress 5Eh, bits 5 to 0, e.g. to be used as source
identifier
double word count: NEP[1], EP[2], DC5 to DC0. DC describes the number of succeeding 32-bit words:
For SAV/EAV mode DC is fixed to 11 double words (byte value 4Bh)
For ANC mode it is: DC = 1⁄4(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to
the chosen text standard
It should be noted that the number of valid bytes inside the stream can be seen in the BC byte.
internal data identification 1: OP[3], FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3 = double word 1 byte 1; see Table 34
internal data identification 2: OP[3], LineNumber2 to LineNumber0, DataType3 to DataType0 = double word 1 byte 2; see Table 34
double word number n, byte number m
last double word byte 4; remark: for SAV/EAV framing DC is fixed to 0Bh, missing data bytes are filled up; the fill value is A0h
the check sum byte, the check sum is accumulated from the SAV (respectively DID) byte to the DDC_4 byte
number of valid sliced bytes counted from the IDI1 byte
end of active data; see Table 34
[1] Inverted EP (bit 7); for EP see Table note 2.
[2] Even parity (bit 6) of bits 5 to 0.
[3] Odd parity (bit 7) of bits 6 to 0.