SAA7108AE Datasheet, PDF (80/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
9.5 Image port output formatter (subaddresses 84h to 87h)
The output interface consists of a FIFO for video and for sliced text data, an arbitration
circuit, which controls the mixed transfer of video and sliced text data over the I port and a
decoding and multiplexing unit, which generates the 8-bit or 16-bit wide output data
stream and the accompanied reference and supporting information.
The clock for the output interface can be derived from an internal clock, decoder,
expansion port or an externally provided clock which is appropriate for e.g. VGA and
frame buffer. The clock can be up to 33 MHz. The scaler provides the following video
related timing reference events (signals), which are available on pins as defined by
subaddresses 84h and 85h:
• Output field ID
• Start and end of vertical active video range
• Start and end of active video line
• Data qualifier or gated clock
• Actually activated programming page (if CONLH is used)
• Threshold controlled FIFO filling flags (empty, full and filled)
• Sliced data marker
The discontinuous data stream at the scaler output is accompanied by a data valid flag (or
data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the
I port data bus (including the HPD pins in 16-bit output mode) are marked with code 00h.
The output interface also arbitrates the transfer between scaled video data and sliced text
data over the I port output.
The bits VITX1 and VITX0 (subaddress 86h) are used to control the arbitration.
As a further operation the serialization of the internal 32-bit double words to 8-bit or
optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV
for video data, ANC or SAV/EAV codes for sliced text data) are done here.
For handshake with the VGA controller, or other memory or bus interface circuitry,
programmable FIFO flags are provided; see Section 9.5.2.
9.5.1 Scaler output formatter (subaddresses 93h and C3h)
The output formatter organizes the packing into the output FIFO. The following formats
are available: Y-C_B-C_R 4 : 2 : 2, Y-C_B-C_R 4 : 1 : 1, Y-C_B-C_R 4 : 2 : 0, Y-C_B-C_R 4 : 1 : 0 and
Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93h[2:0],
FOI[1:0] 93h[4:3] and FYSK[93h[5]].
The data formats are defined on double words, or multiples, and are similar to the video
formats as recommended for PCI multimedia applications (compares to SAA7146A), but
planar formats are not supported.
FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines
are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only
lines will be skipped, and the output will always start with a Y/C line.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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