SAA7108AE Datasheet, PDF (68/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 23. Examples for field processing
Subject
Field sequence frame/field
Example 1^[1] Example 2^[2][3]
1/1 1/2 2/1 1/1 1/2 2/1 2/2
Processed by task A A A B A B A
State of detected
ITU 656 FID
0 1 0 0101
TOGGLE flag
1 0 1 1100
Bit 6 of SAV/EAV
byte
0 1 0 0101
Required sequence
conversion at the
vertical scaler^[8]
UP LO UP UP LO UP LO
↓ ↓ ↓ ↓↓↓↓
UP LO UP UP LO UP LO
Output^[9]
O O O OOOO
Example 3^[2][4][5]
1/1 1/2 2/1 2/2
BBAB
0101
1011
1011
UP LO UP LO
↓↓↓↓
LO UP LO LO
OOOO
3/1 3/2
BA
01
00
00
UP LO
↓↓
UP UP
OO
Example 4^[2][4][6]
1/1 1/2 2/1 2/2
B BAB
0 101
0^[7] 1 1 1^[7]
0^[7] 1 1 1^[7]
UP LO UP LO
↓ ↓↓↓
UP LO LO LO
NO O O NO
3/1 3/2
BA
01
00
00
UP LO
↓↓
UP UP
OO
[1] Single task every field; OFIDC = 0; subaddress 90h at 40h; TEB[80h[5]] = 0.
[2] Tasks are used to scale to different output windows, priority on task B after SWRST.
[3] Both tasks at ¹â„₂ frame rate; OFIDC = 0; subaddresses 90h at 43h and C0h at 42h.
[4] In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.
[5] Task B at ²â„₃ frame rate constructed from neighboring motion phases; task A at ¹â„₃ frame rate of equidistant motion phases; OFIDC = 1;
subaddresses 90h at 41h and C0h at 45h.
[6] Task A and B at ¹â„₃ frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90h at 41h and C0h at 49h.
[7] State of prior field.
[8] It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines.
[9] O = data output; NO = no output.
9.3.2 Horizontal scaling
The overall horizontal required scaling factor has to be split into a binary and a rational
value according to the following equation:
H-scale ratio = ^o--_i--^un---^t-_p-^p--_u--^u-_t--^t---_p-^p--_i--^ix--^x-_e--^e-_l--^l
H-scale ratio = -_X----_P----_S---_C--¹---_[--₅---_:--₀----_] × -_X----_S---_C---¹-_Y--⁰---_[²--₁-⁴--₂---_:--₀----_]
where the parameter of the prescaler XPSC[5:0] = 1 to 63 and the parameter of VPD
phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For
example, ¹â„_3.5 is to split in ¹â„₄ × 1.14286. The binary factor is processed by the prescaler,
the arbitrary non-integer ratio is achieved via the variable phase delay VPD circuitry,
called horizontal fine scaling. The latter calculates horizontally interpolated new samples
with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling
schemes. Prescaler and fine scaler create the horizontal scaler of the SAA7108AE;
SAA7109AE.
Using the accumulation length function of the prescaler (XACL[5:0] A1h[5:0]), application
and destination dependent (e.g. scale for display or for a compression machine), a
compromise between visible bandwidth and alias suppression can be determined.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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