SAA7108AE Datasheet, PDF (60/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
ITU counting
622 623 624 625 1
2
3
4
5
6
7
...
22
23
single field counting 309 310 311 312 1
2
3
4
5
6
7
...
22
23
CVBS
HREF
F_ITU656
V123⁽¹⁾
VGATE
VSTO[8:0] = 134h
FID
(a) 1st field
VSTA[8:0] = 15h
ITU counting
309 310 311 312 313 314 315 316 317 318 319 . . . 335 336
single field counting 309 310 311 312 313 1
2
3
4
5
6
...
22
23
CVBS
HREF
F_ITU656
V123⁽¹⁾
VGATE
VSTO[8:0] = 134h
FID
(b) 2nd field
VSTA[8:0] = 15h
mhb540
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling
edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific
position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to
version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to Table 21.
For further information see Table 160, Table 161 and Table 162.
Fig 33. Vertical timing diagram for 50 Hz/625 line systems
Table 21. Control signals
Name
RTS0 (pin K13)
HREF
X
F_ITU656
-
V123
X
VGATE
X
FID
X
RTS1 (pin L10)
X
-
X
X
X
XRH (pin N2)
X
-
-
-
-
XRV (pin L5)
-
X
X
-
-
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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