SAA7108AE Datasheet, PDF (148/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 159. Mode/delay control; 11h[7:0] …continued
Bit
Description
Symbol
3
polarity of RTS0 output signal RTP0
2 to 0
luminance delay compensation YDEL[2:0]
(steps in 2/LLC)
Value
0
1
100
000
011
Function
non-inverted
inverted
−4...
...0...
...3
11.2.2.19 Subaddress 12h
Table 160. RT signal control: RTS0 output; 12h[3:0]
The polarity of any signal on RTS0 can be inverted via RTP0[11h[3]].
RTS0 output
RTSE03 RTSE02 RTSE01 RTSE00
3-state
0
0
0
0
Constant LOW
0
0
0
1
CREF (13.5 MHz toggling pulse; see Figure 35)
0
0
1
0
CREF2 (6.75 MHz toggling pulse; see Figure 35)
0
0
1
1
HL; horizontal lock indicator^[1]:
0
1
0
0
HL = 0: unlocked
HL = 1: locked
VL; vertical and horizontal lock:
0
1
0
1
VL = 0: unlocked
VL = 1: locked
DL; vertical and horizontal lock and color detected:
0
1
1
0
DL = 0: unlocked
DL = 1: locked
Reserved
0
1
1
1
HREF, horizontal reference signal; indicates 720 pixels 1
0
0
0
valid data on the expansion port. The positive slope
marks the beginning of a new active line. HREF is also
generated during the vertical blanking interval
(see Figure 35).
HS:
1
0
0
1
Programmable width in LLC8 steps via
HSB[7:0] 06h[7:0] and HSS[7:0] 07h[7:0]
Fine position adjustment in LLC2 steps via
HDEL[1:0] 11h[5:4] (see Figure 35)
HQ; HREF gated with VGATE
1
0
1
0
Reserved
1
0
1
1
V123; vertical sync (see vertical timing diagrams
Figure 33 and Figure 34)
1
1
0
0
VGATE; programmable via VSTA[8:0] 17h[0] 15h[7:0], 1
1
0
1
VSTO[8:0] 17h[1] 16h[7:0] and VGPS[17h[2]]
LSBs of the 9-bit ADCs
1
1
1
0
FID; position programmable via VSTA[8:0] 17h[0] 15h[7:0] 1
1
1
1
(see vertical timing diagrams Figure 33 and Figure 34)
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
148 of 208