SAA7108AE Datasheet, PDF (133/208 Pages) NXP Semiconductors – HD-CODEC

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Table 141. I²C-bus receiver/transmitter overview …continued
Register function
Subaddress D7
D6
D5
D4
D3
D2
D1
D0
Reserved
1Ah to 1Eh ^[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Status byte video decoder (read only,
1Fh
OLDSB = 0)
INTL
HLVLN
FIDT
GLIMT
GLIMB
WIPA
COPRO RDCAP
Status byte video decoder (read only,
1Fh
OLDSB = 1)
INTL
HLCK
FIDT
GLIMT
GLIMB
WIPA
SLTCA
CODE
Reserved
20h to 2Fh ^[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Audio clock generator part: registers 30h to 3Fh
Audio master clock cycles per field
30h
ACPF7 ACPF6 ACPF5 ACPF4 ACPF3 ACPF2 ACPF1 ACPF0
31h
ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9 ACPF8
32h
[1]
[1]
[1]
[1]
[1]
[1]
ACPF17 ACPF16
Reserved
33h
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Audio master clock nominal increment
34h
ACNI7
ACNI6
ACNI5
ACNI4
ACNI3
ACNI2
ACNI1
ACNI0
35h
ACNI15 ACNI14 ACNI13 ACNI12 ACNI11 ACNI10 ACNI9
ACNI8
36h
[1]
[1]
ACNI21 ACNI20 ACNI19 ACNI18 ACNI17 ACNI16
Reserved
37h
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Clock ratio AMXCLK to ASCLK
38h
[1]
[1]
SDIV5
SDIV4
SDIV3
SDIV2
SDIV1
SDIV0
Clock ratio ASCLK to ALRCLK
39h
[1]
[1]
LRDIV5 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0
Audio clock generator basic setup
3Ah
[1]
[1]
[1]
[1]
APLL
AMVR
LRPH
SCPH
Reserved
3Bh to 3Fh ^[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
General purpose VBI data slicer part: registers 40h to 7Fh
Slicer control 1
40h
[1]
HAM_N FCE
HUNT_N ^[1]
[1]
[1]
[1]
LCR2 to LCR24 (n = 2 to 24)
41h to 57h LCRn_7 LCRn_6 LCRn_5 LCRn_4 LCRn_3 LCRn_2 LCRn_1 LCRn_0
Programmable framing code
58h
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Horizontal offset for slicer
59h
HOFF7 HOFF6 HOFF5 HOFF4 HOFF3 HOFF2 HOFF1 HOFF0
Vertical offset for slicer
5Ah
VOFF7 VOFF6 VOFF5 VOFF4 VOFF3 VOFF2 VOFF1 VOFF0
Field offset and MSBs for horizontal and 5Bh
vertical offset
FOFF
RECODE ^[1]
VOFF8
[1]
HOFF10 HOFF9 HOFF8
Reserved (for testing)
5Ch
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Header and data identification (DID) code 5Dh
control
FVREF
[1]
DID5
DID4
DID3
DID2
DID1
DID0
Sliced data identification (SDID) code
5Eh
[1]
[1]
SDID5
SDID4
SDID3
SDID2
SDID1
SDID0
Reserved
5Fh
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]