SAA7108AE Datasheet, PDF (75/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
9.3.3.2 Vertical scaler (subaddresses B0h to BFh and E0h to EFh)
Vertical scaling of any ratio from 64 (theoretical zoom) to ¹â„₆₃ (icon) can be applied.
The vertical scaling block consists of another line delay, and the vertical filter structure,
that can operate in two different modes; Linear Phase Interpolation (LPI) and
Accumulation (ACM) mode. These are controlled by YMODE[B4h[0]]:
• LPI mode: In the LPI mode (YMODE = 0) two neighboring lines of the source video
stream are added together, but weighted by factors corresponding to the vertical
position (phase) of the target output line relative to the source lines. This linear
interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It
interpolates between two consecutive input lines only. The LPI mode should be
applied for scaling ratios around 1 (down to ¹â„₂), it must be applied for vertical
zooming.
• ACM mode: The vertical ACM mode (YMODE = 1) represents a vertical averaging
window over multiple lines, sliding over the field. This mode also generates phase
correct output lines. The averaging window length corresponds to the scaling ratio,
resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts.
ACM can be applied for downscales only from ratio 1 down to ¹â„₆₄. ACM results in a
scale dependent DC gain amplification, which has to be precorrected by the BCS
control of the scaler part.
The phase and scale controlling DTO calculates in 16-bit resolution, controlled by
parameters YSCY[15:0] B1h[7:0] B0h[7:0] and YSCC[15:0] B3h[7:0] B2h[7:0],
continuously over the entire field. A start offset can be applied to the phase processing by
means of the parameters YPY3[7:0] to YPY0[7:0] in BFh[7:0] to BCh[7:0] and
YPC3[7:0] to YPC0[7:0] in BBh[7:0] to B8h[7:0]. The start phase covers the range of
255_{⁄32 to} 1_{⁄32 lines offset.}
By programming appropriate, opposite, vertical start phase values (subaddresses
B8h to BFh and E8h to EFh) depending on odd or even field ID of the source video stream
and A or B page cycle, frame ID conversion and field rate conversion are supported (i.e.
de-interlacing, re-interlacing).
Figure 40 and Figure 41 and Table 26 and Table 27 describe the use of the offsets.
Remark: The vertical start phase, as well as the scaling ratio are defined
independently for the luminance and chrominance channel, but must be set to the
same values in the actual implementation for accurate 4 : 2 : 2 output processing.
The vertical processing communicates on its input side with the line FIFO buffer. The
scale related equations are:
• Scaling increment calculation for ACM and LPI mode, downscale and zoom:
YSCY[15:0] and YSCC[15:0] = lower integer of _1024 × -_N-^N---_l--^li--ⁱⁿ--ⁿ-_e--^e-_{_}--^_--_o--ⁱ-_u-ⁿ---_{t}
• BCS value to compensate DC gain in ACM mode (contrast and saturation have to be
set): CONT[7:0] A5h[7:0] respectively SATN[7:0] A6h[7:0]
=
lower
integer
of


-^N-_N---^l--_li--_in--_n-^e--_e-^_--_{_}--^o--_i-^u-_n---^t
×
64_
,
or
=
lower
integer
of


Y^----S^----C^--1--Y^-0---[^2--1^-4--5^----:^--0^---]^-
×
64_
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
75 of 208