SAA7108AE Datasheet, PDF (120/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
SAA7108AE_SAA7109AE_3
Product data sheet
Table 90. FIFO control register, subaddress 85h, bit description
Legend: * = default value after reset, ^ = nominal value.
Bit
Symbol Access Value Description
7
EIDIV R/W 0* DVO compliant signals are applied
1
non-DVO compliant signals are applied
6 to 4 -
R/W 000 must be programmed with logic 0 to ensure compatibility to
future enhancements
3 to 0 FILI[3:0] R/W 8h*^ threshold for FIFO internal transfers
Table 91. Horizontal offset register, subaddress 90h, bit description
Bit
Symbol
Description
7 to 0
XOFS[7:0]
with XOFS[9:8] (see Table 95) horizontal offset; defines the number of
PIXCLKs from horizontal sync (HSVGC) output to composite blanking
(CBO) output
Table 92. Pixel number register, subaddress 91h, bit description
Bit
Symbol
Description
7 to 0 XPIX[7:0]
with XPIX[9:8] (see Table 95) pixel in X direction; defines half the number
of active pixels per input line (identical to the length of CBO pulses)
Table 93. Vertical offset odd register, subaddress 92h, bit description
Bit
Symbol
Description
7 to 0
YOFSO[7:0]
with YOFSO[9:8] (see Table 95) vertical offset in odd field; defines (in the
odd field) the number of lines from VSVGC to first line with active CBO; if
no LUT data is requested, the first active CBO will be output at
YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme
vertical downscaling and interlacing
Table 94. Vertical offset even register, subaddress 93h, bit description
Bit
Symbol
Description
7 to 0
YOFSE[7:0]
with YOFSE[9:8] (see Table 95) vertical offset in even field; defines (in the
even field) the number of lines from VSVGC to first line with active CBO; if
no LUT data is requested, the first active CBO will be output at
YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme
vertical downscaling and interlacing
Table 95. MSBs register, subaddress 94h, bit description
Bit
Symbol
Description
7 and 6 YOFSE[9:8] see Table 94
5 and 4 YOFSO[9:8] see Table 93
3 and 2 XPIX[9:8] see Table 92
1 and 0 XOFS[9:8] see Table 91
Table 96. Line number register, subaddress 95h, bit description
Bit
Symbol
Description
7 to 0 YPIX[7:0]
with YPIX[9:8] (see Table 97) defines the number of requested input lines
from the feeding device; number of requested
lines = YPIX + YOFSE − YOFSO
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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