SAA7108AE Datasheet, PDF (28/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
8.17 Pattern generator for HD sync pulses
The pattern generator provides appropriate synchronization patterns for the video data
path in auxiliary monitor or HDTV mode. It provides maximum flexibility in terms of raster
generation for all interlaced and non-interlaced computer graphics or ATSC formats. The
sync engine is capable of providing a combination of event-value pairs which can be used
to insert certain values in the outgoing data stream at specified times. It can also be used
to generate digital signals associated with time events. These can be used as digital
horizontal and vertical synchronization signals on pins HSM_CSYNC and VSM.
The picture position is adjustable through the programmable relationship between the
sync pulses and the video contents.
The generation of embedded analog sync pulses is bound to a number of events which
can be defined for a line. Several of these line timing definitions can exist in parallel. For
the final sync raster composition a certain sequence of lines with different sync event
properties has to be defined. The sequence specifies a series of line types and the
number of occurrences of this specific line type. Once the sequence has been completed,
it restarts from the beginning. All pulse shapes are filtered internally in order to avoid
ringing after analog post filters.
The sequence of the generated pulse stream must fit precisely to the incoming data
stream in terms of the total number of pixels per line and lines per frame.
The sync engines flexibility is achieved by using a sequence of linked lists carrying the
properties for the image, the lines as well as fractions of lines. Figure 12 illustrates the
context between the various tables.
The first table serves as an array to hold the correct sequence of lines that compose the
synchronization raster; it can contain up to 16 entries. Each entry holds a 4-bit index to
the next table and a 10-bit counter value which specifies how often this particular line is
invoked. If the necessary line count for a particular line exceeds the 10 bits, it has to use
two table entries.
The 4-bit index in the line count array points to the line type array. It holds up to 15 entries
(index 0 is not used), index 1 points to the first entry, index 2 to the second entry of the line
type array etc.
Each entry of the line type array can hold up to 8 index pointers to another table. These
indices point to portions of a line pulse pattern: A line could be split up e.g. into a sync, a
blank, and an active portion followed by another blank portion, occupying four entries in
one table line.
Each index of this table points to a particular line of the next table in the linked list. This
table is called the line pattern array and each of the up to seven entries stores up to four
pairs of a duration in pixel clock cycles and an index to a value table. The table entries are
used to define portions of a line representing a certain value for a certain number of clock
cycles.
The value specified in this table is actually another 3-bit index into a value array which can
hold up to eight 8-bit values. If bit 4 (MSB) of the index is logic 1, the value is inserted into
the G or Y signal only; if bit 4 = 0, the associated value is inserted into all three signals.
SAA7108AE_SAA7109AE_3
Product data sheet
Two additional bits of the entries in the value array (LSBs of the second byte) determine if
the associated events appear as a digital pulse on the HSM_CSYNC and/or VSM outputs.
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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