SAA7108AE Datasheet, PDF (25/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Chrominance is modified in gain (programmable separately for C_B and C_R), and a
standard dependent burst is inserted, before baseband color signals are interpolated from
a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be
bypassed, thus providing a higher color bandwidth, which can be used for the Y and C
output. The transfer characteristics of the chrominance interpolation filter are illustrated in
Figure 6 and Figure 7.
The amplitude (beginning and ending) of the inserted burst, is programmable in a certain
range that is suitable for standard signals and for special effects. After the succeeding
quadrature modulator, color is provided on the subcarrier in 10-bit resolution.
The numeric ratio between the Y and C outputs is in accordance with the standards.
8.12.2 Teletext insertion and encoding (not simultaneously with real-time control)
Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock.
At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided
after a programmable delay at input pin TTX_SRES.
Phase variant interpolation is achieved on this bitstream in the internal teletext encoder,
providing sufficient small phase jitter on the output text lines.
TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source,
indicating the insertion period of bitstream at lines which can be selected independently
for both fields. The internal insertion window for text is set to 360 (PAL WST),
296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol
and timing are illustrated in Figure 66.
Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.
8.12.3 Video Programming System (VPS) encoding
Five bytes of VPS information can be loaded via the I²C-bus and will be encoded in the
appropriate format into line 16.
8.12.4 Closed caption encoder
Using this circuit, data in accordance with the specification of closed caption or extended
data service, delivered by the control interface, can be encoded (line 21). Two dedicated
pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code,
are possible.
The actual line number in which data is to be encoded, can be modified in a certain range.
The data clock frequency is in accordance with the definition for NTSC M standard
32 times horizontal line frequency.
Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the
DACs corresponds to approximately 50 IRE.
It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times the
horizontal line frequency.
8.12.5 Anti-taping (SAA7108AE only)
For more information contact your nearest NXP Semiconductors sales office.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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