SAA7108AE Datasheet, PDF (134/208 Pages) NXP Semiconductors – HD-CODEC

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Table 141. I²C-bus receiver/transmitter overview …continued
Register function
Subaddress D7
D6
D5
D4
D3
D2
D1
D0
Slicer status byte 0 (read only)
60h
-
FC8V
FC7V
VPSV
PPV
CCV
-
-
Slicer status byte 1 (read only)
61h
-
-
F21_N
LN8
LN7
LN6
LN5
LN4
Slicer status byte 2 (read only)
62h
LN3
LN2
LN1
LN0
DT3
DT2
DT1
DT0
Reserved
63h to 7Fh ^[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
X port, I port and the scaler part: registers 80h to EFh
Task independent global settings: 80h to 8Fh
Global control 1
80h
[1]
SMOD
TEB
TEA
ICKS3
ICKS2
ICKS1
ICKS0
Reserved
81h and 82h ^[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
X port I/O enable and output clock phase 83h
[1]
[1]
XPCK1
XPCK0
[1]
XRQT
XPE1
XPE0
control
I port signal definitions
84h
IDG01
IDG00
IDG11
IDG10
IDV1
IDV0
IDH1
IDH0
I port signal polarities
85h
ISWP1
ISWP0
ILLV
IG0P
IG1P
IRVP
IRHP
IDQP
I port FIFO flag control and arbitration
86h
VITX1
VITX0
IDG02
IDG12
FFL1
FFL0
FEL1
FEL0
I port I/O enable, output clock and gated 87h
IPCK3
IPCK2
IPCK1
IPCK0
[1]
[1]
IPE1
IPE0
clock phase control
Power save control
88h
CH4EN CH2EN SWRST DPROG SLM3
[1]
SLM1
SLM0
Reserved
89h to 8Eh ^[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Status information scaler part
8Fh
XTRI
ITRI
FFIL
FFOV
PRDON ERROF FIDSCI FIDSCO
Task A definition: registers 90h to BFh
Basic settings and acquisition window definition
Task handling control
90h
CONLH OFIDC
FSKP2
FSKP1
FSKP0
RPTSK STRC1
STRC0
X port formats and configuration
91h
CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2
FSC1
FSC0
X port input reference signal definitions 92h
XFDV
XFDH
XDV1
XDV0
XCODE XDH
XDQ
XCKS
I port output formats and configuration
93h
ICODE I8_16
FYSK
FOI1
FOI0
FSI2
FSI1
FSI0
Horizontal input window start
94h
XO7
XO6
XO5
XO4
XO3
XO2
XO1
XO0
95h
[1]
[1]
[1]
[1]
XO11
XO10
XO9
XO8
Horizontal input window length
96h
XS7
XS6
XS5
XS4
XS3
XS2
XS1
XS0
97h
[1]
[1]
[1]
[1]
XS11
XS10
XS9
XS8
Vertical input window start
98h
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
99h
[1]
[1]
[1]
[1]
YO11
YO10
YO9
YO8