SAA7108AE Datasheet, PDF (150/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.2.20 Subaddress 13h
Table 162. RT/X port output control; 13h[7:0]
Bit
Description
Symbol
7
RTCO output enable RTCE
6
X port XRH output
XRHS
selection
5 and 4 X port XRV output
selection
XRVS[1:0]
3
2 to 0
horizontal lock
indicator selection
XPD7 to XPD0 (port
output format
selection); see
Section 10.4
HLSEL
OFTS[2:0]
Value
0
1
0
1
00
01
10
11
0
1
000
001
010
011
100
101
110
111
Function
3-state
enabled
HREF (see Figure 35)
HS:
Programmable width in LLC8 steps via HSB[7:0] 06h[7:0]
and HSS[7:0] 07h[7:0]
Fine position adjustment in LLC2 steps via HDEL[1:0]
11h[5:4] (see Figure 35)
V123 (see Figure 33 and Figure 34)
ITU 656 related field ID (see Figure 33 and Figure 34)
inverted V123
inverted ITU 656 related field ID
copy of inverted HLCK status bit (default)
fast horizontal lock indicator (for special applications only)
ITU 656
ITU 656-like format with modified field blanking according to
VGATE position (programmable via VSTA[8:0] 17h[0]
15h[7:0], VSTO[8:0] 17h[1] 16h[7:0] and VGPS[17h[2]])
Y-C_B-C_R 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted)
reserved
multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on mode
settings (see Section 11.2.2.3); if both ADCs are selected
AD2 is output at CREF = 1 and AD1 is output at CREF = 0
multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on mode
settings (see Section 11.2.2.3); if both ADCs are selected
AD2 is output at CREF = 1 and AD1 is output at CREF = 0
reserved
multiplexed ADC MSB/LSB bypass dependent on mode
settings; only one ADC should be selected at a time;
ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0
are outputs at CREF = 0
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
150 of 208