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| SAA7108AE Datasheet, PDF (138/208 Pages) NXP Semiconductors – HD-CODEC | |||
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NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.2 I2C-bus details
11.2.2.1 Subaddress 00h
Table 142. Chip Version (CV) identiï¬cation; 00h[7:4]; read only register
Function
Logic levels
ID7
ID6
ID5
ID4
Chip Version (CV)
CV3
CV2
CV1
CV0
11.2.2.2 Subaddress 01h
The programming of the horizontal increment delay is used to match internal processing
delays to the delay of the ADC. Use recommended position only.
Table 143. Horizontal increment delay; 01h[3:0]
Function
IDEL3
No update
1
Minimum delay
1
Recommended position
1
Maximum delay
0
IDEL2
1
1
0
0
IDEL1
1
1
0
0
IDEL0
1
0
0
0
11.2.2.3 Subaddress 02h
Table 144. Analog input control 1 (AICO1); 02h[7:0]
Bit
Description
Symbol Value Function
7 and 6 analog function
select;
see Figure 16
FUSE[1:0] 00
01
10
ampliï¬er plus anti-alias ï¬lter bypassed
ampliï¬er plus anti-alias ï¬lter bypassed
ampliï¬er active
11 ampliï¬er plus anti-alias ï¬lter active
5 and 4 update hysteresis GUDL[1:0] 00
for 9-bit gain;
01
see Figure 17
10
off
±1 LSB
±2 LSB
11 ±3 LSB
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 â 6 February 2007
© NXP B.V. 2007. All rights reserved.
138 of 208
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