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SAA7108AE Datasheet, PDF (36/208 Pages) NXP Semiconductors – HD-CODEC
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NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
SAA7108AE_SAA7109AE_3
Product data sheet
Table 13. Pin assignment for input format 1
5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB
Pin
Falling clock edge
PD7
G2
PD6
G1
PD5
G0
PD4
B4
PD3
B3
PD2
B2
PD1
B1
PD0
B0
Rising clock edge
X
R4
R3
R2
R1
R0
G4
G3
Table 14. Pin assignment for input format 2
5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB
Pin
Falling clock edge
PD7
G2
PD6
G1
PD5
G0
PD4
B4
PD3
B3
PD2
B2
PD1
B1
PD0
B0
Rising clock edge
R4
R3
R2
R1
R0
G5
G4
G3
Table 15. Pin assignment for input format 3
8 + 8 + 8-bit 4 : 2 : 2 non-interlaced CB-Y-CR
Pin
Falling clock
Rising clock
edge n
edge n
PD7
CB7(0)
Y7(0)
PD6
CB6(0)
Y6(0)
PD5
CB5(0)
Y5(0)
PD4
CB4(0)
Y4(0)
PD3
CB3(0)
Y3(0)
PD2
CB2(0)
Y2(0)
PD1
CB1(0)
Y1(0)
PD0
CB0(0)
Y0(0)
Falling clock
edge n + 1
CR7(0)
CR6(0)
CR5(0)
CR4(0)
CR3(0)
CR2(0)
CR1(0)
CR0(0)
Rising clock
edge n + 1
Y7(1)
Y6(1)
Y5(1)
Y4(1)
Y3(1)
Y2(1)
Y1(1)
Y0(1)
Table 16. Pin assignment for input format 4
8 + 8 + 8-bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock)
Pin
Rising clock
Rising clock
Rising clock
edge n
edge n + 1
edge n + 2
PD7
PD6
PD5
CB7(0)
CB6(0)
CB5(0)
Y7(0)
Y6(0)
Y5(0)
CR7(0)
CR6(0)
CR5(0)
Rev. 03 — 6 February 2007
Rising clock
edge n + 3
Y7(1)
Y6(1)
Y5(1)
© NXP B.V. 2007. All rights reserved.
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