SAA7108AE Datasheet, PDF (92/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
The data type selections by LCR are overruled by setting OFTS2 = 1 (subaddress 13h
bit 2). This setting is mainly intended for device production testing. The VPO-bus carries
the upper or lower 8 bits of the two ADCs depending on the OFTS[1:0] 13h[1:0] settings;
see Table 162. The input configuration is done via MODE[3:0] 02h[3:0] settings; see
Table 144. If a Y/C mode is selected, the expansion port carries the multiplexed output
signals of both ADCs, and in CVBS mode the output of only one ADC. No timing reference
codes are generated in this mode.
Remark: The LSBs (bit 0) of the ADCs are also available on pin RTS0; see Table 160.
The SAV/EAV timing reference codes define the start and end of valid data regions. The
ITU-blanking code sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the horizontal
blanking period between EAV and SAV.
The position of the F-bit is constant in accordance with ITU 656; see Table 44 and
Table 45.
The V-bit can be generated in two different ways (see Table 44 and Table 45) controlled
via OFTS1 and OFTS0; see Table 162.
The F and V bits change synchronously with the EAV code.
Table 42. Data format on the expansion port
Blanking
period
Timing reference 720 pixels Y-C_B-C_R 4 : 2 : 2 data^[2]
code
(hexadecimal)^[1]
Timing reference Blanking
code
period
(hexadecimal)^[1]
... 80 10 FF 00 00 SAV C_B0 Y0 C_R0 Y1 C_B2 Y2 ... C_R718 Y719 FF 00 00 EAV 80 10 ...
[1] The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to ‘010’; see Table 162. In this event the code
sequence is replaced by the standard ‘- 80 - 10 -’ blanking values.
[2] If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced by CVBS samples.
Table 43.
Bit
7
6
5
4
3 to 0
SAV/EAV format on expansion port XPD7 to XPD0
Symbol
Description
logic 1
F
field bit
1st field: F = 0
2nd field: F = 1
for vertical timing see Table 44 and Table 45
V
vertical blanking bit
VBI: V = 1
active video: V = 0
for vertical timing see Table 44 and Table 45
H
format
H = 0 in SAV format
H = 1 in EAV format
P[3:0]
reserved; evaluation not recommended (protection bits according to ITU-R BT 656)
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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