SAA7108AE Datasheet, PDF (55/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
+255
+209
white
+255
+199
white
LUMINANCE
LUMINANCE
+71
black
+60
black shoulder
SYNC
1
sync bottom
001aac244
+60
black shoulder = black
SYNC
1
sync bottom
001aac245
CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128.
Equation for modification of the raw data levels via bytes RAWG and RAWO:
CVBS_OUT = Int -^R----^A-₆---^W4-----^G--- × (CVBS_nom – 128) + RAWO
It should be noted that the resulting levels are limited to 1 to 254 in accordance with
‘ITU Recommendation 601/656’.
a. Sources containing 7.5 IRE black level
offset (e.g. NTSC M).
b. Sources not containing black level
offset.
Fig 28. CVBS (raw data) range for scaler input, data slicer and X port output
9.1.4 Synchronization
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is
further reduced to 1 MHz by a low-pass filter. The sync pulses are sliced and fed to the
phase detectors where they are compared with the sub-divided clock frequency. The
resulting output signal is applied to the loop filter to accumulate all phase deviations.
Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to generate the line frequency
control signal LFCO; see Figure 29.
The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is
also achieved within the synchronization circuit.
The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh.
9.1.5 Clock generation circuit
The internal CGC generates all clock signals required for the video input processor.
The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal
PLL. It is the multiple of the line frequency:
SAA7108AE_SAA7109AE_3
Product data sheet
• 6.75 MHz = 429 × f_H (50 Hz), or
• 6.75 MHz = 432 × f_H (60 Hz)
The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including
phase detector, loop filtering, VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50 % duty factor.
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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