SAA7108AE Datasheet, PDF (157/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.4.8 Subaddress 5Eh
Table 182. Sliced data identification (SDID) code; slicer set 5Eh[5:0]
Bit
Description
Symbol Value Function
5 to 0 SDID codes
SDID[5:0] 00h
default
11.2.4.9 Subaddress 60h
Table 183. Slicer status byte 0; 60h[6:2]; read only register
Bit
Description
Symbol Value Function
6
framing code valid FC8V 0
no framing code (0 error) in the last frame
detected
1
framing code with 0 error detected
5
framing code valid FC7V 0
no framing code (1 error) in the last frame
detected
1
framing code with 1 error detected
4
VPS valid
VPSV 0
no VPS in the last frame
1
VPS detected
3
PALplus valid
PPV 0
no PALplus in the last frame
1
PALplus detected
2
closed caption valid CCV 0
no closed caption in the last frame
1
closed caption detected
11.2.4.10 Subaddresses 61h and 62h
Table 184. Slicer status byte 1; 61h[5:0] and slicer status byte 2; 62h[7:0]; read only
registers
Subaddress Bit
Symbol Description
61h
5
F21_N field ID as seen by the VBI slicer; for field 1: bit 5 = 0
4 to 0
LN[8:4] line number
62h
7 to 4
LN[3:0] line number
3 to 0
DT[3:0] data type; according to Table 28
11.2.5 Programming register interfaces and scaler part
11.2.5.1 Subaddress 80h
Table 185. Global control 1; global set 80h[6:4]^[1]
SWRST moved to subaddress 88h[5].
Task enable control
Control bits 6 to 4
SMOD TEB
TEA
Task of register set A is disabled
X
X
0
Task of register set A is enabled
X
X
1
Task of register set B is disabled
X
0
X
Task of register set B is enabled
X
1
X
The scaler window defines the F and V timing of the scaler output 0
X
X
VBI data slicer defines the F and V timing of the scaler output
1
X
X
[1] X = don’t care.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
157 of 208