SAA7108AE Datasheet, PDF (117/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 78. TTX request horizontal delay register, subaddress 74h, bit description
Legend: * = default value after reset and minimum value.
Bit Symbol
Access Value Description
7 to 4 -
R/W 0h must be programmed with logic 0 to ensure compatibility
to future enhancements
3 to 0 TTXHD[3:0] R/W
2h* indicates the delay in clock cycles between rising edge of
TTXRQ output signal on pin TTXRQ_XCLKO2
(CLK2EN = 0) and valid data at pin TTX_SRES
Table 79. CSYNC advance register, subaddress 75h, bit description
Bit Symbol
Access Value Description
7 to 3 CSYNCA[4:0] R/W -
advanced composite sync against RGB output from
0 XTAL clocks to 31 XTAL clocks
2 to 0 -
R/W 000 must be programmed with logic 0 to ensure compatibility
to future enhancements
Table 80. TTX odd request vertical start register, subaddress 76h, bit description
Legend: * = default value after reset.
Bit Symbol
Access Value Description
7 to 0 TTXOVS[7:0] R/W
with TTXOVS8 (see Table 86) first line of occurrence of
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
odd field, line = (TTXOVS + 4) for M-systems and
line = (TTXOVS + 1) for other systems
05h* if strapped to PAL
06h* if strapped to NTSC
Table 81. TTX odd request vertical end register, subaddress 77h, bit description
Legend: * = default value after reset.
Bit Symbol
Access Value Description
7 to 0 TTXOVE[7:0] R/W
with TTXOVE8 (see Table 86) last line of occurrence of
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
odd field, line = (TTXOVE + 3) for M-systems and
line = TTXOVE for other systems
16h* if strapped to PAL
10h* if strapped to NTSC
Table 82. TTX even request vertical start register, subaddress 78h, bit description
Legend: * = default value after reset.
Bit Symbol
Access Value Description
7 to 0 TTXEVS[7:0] R/W
with TTXEVS8 (see Table 86) first line of occurrence of
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
even field, line = (TTXEVS + 4) for M-systems and
line = (TTXEVS + 1) for other systems
04h* if strapped to PAL
05h* if strapped to NTSC
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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