SAA7108AE Datasheet, PDF (152/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.2.23 Subaddress 16h
Table 165. VGATE stop; 17h[1] and 16h[7:0]
Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figure 33 and Figure 34.
Field
Frame
line
counting
Decimal
value
MSB
17h[1]
VSTO8
Control bits 7 to 0
VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0
50 Hz 1st 1
312
1
0
0
1
1
1
0
0
0
2nd 314
1st 2
0...
0
0
0
0
0
0
0
0
0
2nd 315
1st 312
...310 1
0
0
1
1
0
1
1
1
2nd 625
60 Hz 1st 4
262
1
0
0
0
0
0
1
1
0
2nd 267
1st 5
0...
0
0
0
0
0
0
0
0
0
2nd 268
1st 265
...260 1
0
0
0
0
0
1
0
1
2nd 3
11.2.2.24 Subaddress 17h
Table 166. Miscellaneous/VGATE MSBs; 17h[7:6] and 17h[2:0]
Bit
Description
Symbol
Value Function
7
LLC output enable
LLCE
0
enable
1
3-state
6
LLC2 output enable
LLC2E
0
enable
1
3-state
2
alternative VGATE position VGPS
0
VGATE position according to Table 164 and
Table 165
1
VGATE occurs one line earlier during field 2
1
MSB VGATE stop
VSTO8
see Table 165
0
MSB VGATE start
VSTA8
see Table 164
11.2.2.25 Subaddress 18h
Table 167. Raw data gain control; RAWG[7:0] 18h[7:0]; see Figure 28
Gain
Control bits 7 to 0
RAWG7 RAWG6 RAWG5 RAWG4 RAWG3
255 (double amplitude) 0
1
1
1
1
128 (nominal level)
0
1
0
0
0
0 (off)
0
0
0
0
0
RAWG2
1
0
0
RAWG1
1
0
0
RAWG0
1
0
0
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
152 of 208