SAA7108AE Datasheet, PDF (63/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
9.3 Scaler
The High Performance video Scaler (HPS) is based on the system as implemented in
previous products (e.g. SAA7140), but with some aspects enhanced. Vertical upsampling
is supported and the processing pipeline buffer capacity is enhanced, to allow more
flexible video stream timing at the image port, discontinuous transfers and handshake.
The internal data flow from block to block is discontinuous dynamically, due to the scaling
process.
The flow is controlled by internal data valid and data request flags (internal handshake
signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer.
Depending on the actual programmed scaling parameters the effective buffer can exceed
to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced
significantly.
The high performance video scaler in the SAA7108AE; SAA7109AE has the following
major blocks:
• Acquisition control (horizontal and vertical timer) and task handling (the
region/field/frame based processing)
• Prescaler, for horizontal downscaling by an integer factor, combined with appropriate
band limiting filters, especially anti-aliasing for CIF format
• Brightness, saturation and contrast control for scaled output data
• Line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for
videophone application, converting 240 into 288 lines, Y-C_B-C_R 4 : 2 : 2)
• Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and
downscale, or phase accurate Accumulation Mode (ACM) for large downscaling ratios
and better anti-alias suppression
• Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for
arbitrary non-integer scaling ratios, supporting conversion between square and
rectangular pixel sampling
• Output formatter for scaled Y-C_B-C_R 4 : 2 : 2, Y-C_B-C_R 4 : 1 : 1 and Y only (format also
used for raw data)
• FIFO, 32-bit wide, with 64 pixel capacity in Y-C_B-C_R formats
• Output interface, 8-bit or 16-bit (only if extended by H port) data pins wide,
synchronous or asynchronous operation, with stream events on discrete pins, or
coded in the data stream
The overall H and V zooming (HV_zoom) is restricted by the input/output data rate
relationships. With a safety margin of 2 % for running in and running out, the maximum
HV_zoom is equal to: 0.98 × _i---_n---_{_}----_p---_i--_x---_e---_l---_×-----_i-^T-_n----_{__}---_li--_in--_n-^p--_e--^u-_s--^t--_×^_-----^fo--ⁱ-_u-^e---^lt--^d_{_}---_c-^–--_y---^Tc---_l-^_-_e--^v-_{_}--^_--_p--^b--_e-^l--_ra--_{_}--ⁿ--_p-^k---_ii--_xn---^g-_×-----_T----_{_}---_o----_u---_t--_{_}---_c---_l--_k-
For example:
1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate,
1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum
HV_zoom is equal to: 0.98 × ₇---²²---⁰⁰-----_×-^m----_2s---₈-^–--₈---²-_×--⁴---₂-^×----_×-⁶---⁴³---₇--^µ---_n-^s---_s- = 1.18
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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