SAA7108AE Datasheet, PDF (136/208 Pages) NXP Semiconductors – HD-CODEC

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Table 141. I²C-bus receiver/transmitter overview …continued
Register function
Subaddress D7
D6
D5
D4
D3
D2
D1
D0
Vertical chrominance phase offset ‘00’
B8h
YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00
Vertical chrominance phase offset ‘01’
B9h
YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10
Vertical chrominance phase offset ‘10’
BAh
YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20
Vertical chrominance phase offset ‘11’
BBh
YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30
Vertical luminance phase offset ‘00’
BCh
YPY07
YPY06
YPY05
YPY04
YPY03
YPY02
YPY01
YPY00
Vertical luminance phase offset ‘01’
BDh
YPY17
YPY16
YPY15
YPY14
YPY13
YPY12
YPY11
YPY10
Vertical luminance phase offset ‘10’
BEh
YPY27
YPY26
YPY25
YPY24
YPY23
YPY22
YPY21
YPY20
Vertical luminance phase offset ‘11’
BFh
YPY37
YPY36
YPY35
YPY34
YPY33
YPY32
YPY31
YPY30
Task B definition registers C0h to EFh
Basic settings and acquisition window definition
Task handling control
C0h
CONLH OFIDC
FSKP2
FSKP1
FSKP0
RPTSK STRC1
STRC0
X port formats and configuration
C1h
CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2
FSC1
FSC0
Input reference signal definition
C2h
XFDV
XFDH
XDV1
XDV0
XCODE XDH
XDQ
XCKS
I port formats and configuration
C3h
ICODE I8_16
FYSK
FOI1
FOI0
FSI2
FSI1
FSI0
Horizontal input window start
C4h
XO7
XO6
XO5
XO4
XO3
XO2
XO1
XO0
C5h
[1]
[1]
[1]
[1]
XO11
XO10
XO9
XO8
Horizontal input window length
C6h
XS7
XS6
XS5
XS4
XS3
XS2
XS1
XS0
C7h
[1]
[1]
[1]
[1]
XS11
XS10
XS9
XS8
Vertical input window start
C8h
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
C9h
[1]
[1]
[1]
[1]
YO11
YO10
YO9
YO8
Vertical input window length
CAh
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
CBh
[1]
[1]
[1]
[1]
YS11
YS10
YS9
YS8
Horizontal output window length
CCh
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
CDh
[1]
[1]
[1]
[1]
XD11
XD10
XD9
XD8
Vertical output window length
CEh
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
CFh
[1]
[1]
[1]
[1]
YD11
YD10
YD9
YD8
FIR filtering and prescaling
Horizontal prescaling
D0h
[1]
[1]
XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0
Accumulation length
D1h
[1]
[1]
XACL5
XACL4
XACL3
XACL2
XACL1
XACL0
Prescaler DC gain and FIR prefilter control D2h
PFUV1 PFUV0 PFY1
PFY0
XC2_1
XDCG2 XDCG1 XDCG0
Reserved
D3h
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]