SAA7108AE Datasheet, PDF (95/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
SAA7108AE_SAA7109AE_3
Product data sheet
• There may be more or less than 720 pixels between SAV and EAV
• Data content and number of clock cycles during horizontal and vertical blanking is
undefined, and may not be constant
• Data stream may be interleaved with not-valid data codes, 00h, but SAV and EAV
4-byte codes are not interleaved with not-valid data codes
• There may be an irregular pattern of not-valid data, or IDQ, and as a result, C_B-Y-C_R-Y
is not in a fixed phase to a regular clock divider
• VBI raw sample streams are enveloped with SAV and EAV, like normal video
• Decoded VBI data is transported as Ancillary (ANC) data, two modes:
– Direct decoded VBI data bytes (8-bit) are directly placed in the ANC data field,
00h and FFh codes may appear in the data block (violation to ITU-R BT.656)
– Recoded VBI data bytes (8-bit) directly placed in ANC data field, 00h and FFh
codes will be recoded to even parity codes 03h and FCh to suppress invalid
ITU-R BT.656 codes
There are no empty cycles in the ancillary code and its data field. The data codes
00h and FFh are suppressed (changed to 01h or FEh respectively) in the active video
stream, as well as in the VBI raw sample stream (VBI pass-through). Optionally, the
number range can be further limited.
Table 46. Signals dedicated to the image port
Symbol Pin
I/O Description
Bit
IPD7 to
IPD0
E14, D14, O
C14, B14,
E13, D13,
C13 and B13
I port data
ICODE[93h[7]],
ISWP[1:0] 85h[7:6]
and
IPE[1:0] 87h[1:0]
ICLK H12
I/O continuous reference clock at image port,
can be input or output, as output decoder
LLC or XCLK from X port
ICKS[1:0] 80h[1:0]
and
IPE[1:0] 87h[1:0]
IDQ
H14
O data valid flag at image port, qualifier, with ICKS2[80h[2]],
programmable polarity; secondary function: IDQP[85h[0]] and
gated clock
IPE[1:0] 87h[1:0]
IGPH G12
O horizontal reference output signal, copy of IDH[1:0] 84h[1:0],
the horizontal gate signal of the scaler, with IRHP[85h[1]] and
programmable polarity; alternative function: IPE[1:0] 87h[1:0]
HRESET pulse
IGPV F13
O vertical reference output signal, copy of the IDV[1:0] 84h[3:2],
vertical gate signal of the scaler, with
IRVP[85h[2]] and
programmable polarity; alternative function: IPE[1:0] 87h[1:0]
VRESET pulse
IGP1 G13
O general purpose output signal for I port
IDG12[86h[4]],
IDG1[1:0] 84h[5:4],
IG1P[85h[3]] and
IPE[1:0] 87h[1:0]
IGP0 F14
O general purpose output signal for I port
IDG02[86h[5]],
IDG0[1:0] 84h[7:6],
IG0P[85h[4]] and
IPE[1:0] 87h[1:0]
ITRDY J14
I target ready input signals
-
ITRI G14
I port control, switches I port into 3-state
IPE[1:0] 87h[1:0]
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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