SAA7108AE Datasheet, PDF (151/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.2.21 Subaddress 14h
Table 163. Analog/ADC/compatibility control; 14h[7:0]
Bit
Description
Symbol
7
compatibility bit for SAA7199 CM99
6
5 and 4
update time interval for AGC UPTCV
value
analog test select
AOSL[1:0]
3
2
1 and 0
XTOUTd output enable
XTOUTE
decoder status byte selection; OLDSB
see Table 169
ADC sample clock phase
delay
APCK[1:0]
Value
0
1
0
1
00
01
10
11
0
1
0
1
00
01
10
11
Function
off (default)
on (to be set only if SAA7199 is used for
re-encoding in conjunction with RTCO active)
horizontal update (once per line)
vertical update (once per field)
AOUT connected to internal test point 1
AOUT connected to input AD1
AOUT connected to input AD2
AOUT connected to internal test point 2
pin P4 (XTOUTd) 3-stated
pin P4 (XTOUTd) enabled
standard
backward compatibility to SAA7112
application dependent
application dependent
application dependent
application dependent
11.2.2.22 Subaddress 15h
Table 164. VGATE start; FID polarity change; 17h[0] and 15h[7:0]
Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figure 33 and Figure 34.
Field
Frame
line
counting
Decimal
value
MSB
17h[0]
VSTA8
Control bits 7 to 0
VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0
50 Hz 1st 1
312
1
0
0
1
1
1
0
0
0
2nd 314
1st 2
0...
0
0
0
0
0
0
0
0
0
2nd 315
1st 312
...310 1
0
0
1
1
0
1
1
1
2nd 625
60 Hz 1st 4
262
1
0
0
0
0
0
1
1
0
2nd 267
1st 5
0...
0
0
0
0
0
0
0
0
0
2nd 268
1st 265
...260 1
0
0
0
0
0
1
0
1
2nd 3
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
151 of 208