SAA7108AE Datasheet, PDF (31/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 9. Example for setup of the sync tables …continued
Sequence (hexadecimal) Comment
80 00
null (identical to sync level LOW)
Write to subaddress DCh
0B
insertion is active, gain for signal is adapted accordingly
8.18 I²C-bus interface
The I²C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses
and 400 kbit/s guaranteed transfer rate. It uses 8-bit subaddressing with an
auto-increment function. All registers are write and read, except two read only status
bytes.
The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and
control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is
assigned to one address. Thus a write access needs the LUT address and three data
bytes following subaddress FFh. For further write access auto-incrementing of the LUT
address is performed. The cursor bit map access is similar to the LUT access but contains
only a single byte per address.
The I²C-bus slave address is defined as 88h.
8.19 Power-down modes
In order to reduce the power consumption, the SAA7108AE; SAA7109AE supports
2 Power-down modes, accessible via the I²C-bus. The analog Power-down mode
(DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer.
The digital Power-down mode (DOWND = 1) turns off all internal clocks and sets the
digital outputs to LOW except the I²C-bus interface. The IC keeps its programming and
can still be accessed in this mode, however not all registers can be read from or written to.
Reading or writing to the look-up tables, the cursor and the HD sync generator require a
valid pixel clock. The typical supply current in full power-down is approximately 5 mA.
Because the analog Power-down mode turns off the pixel clock synthesizer, there are
limitations in some applications. If there is no pixel clock, the IC is not able to set its
outputs to LOW. So, in most cases, DOWNA and DOWND should be set to logic 1
simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down.
8.20 Programming the graphics acquisition scaler of the video encoder
The encoder section needs to provide a continuous data stream at its analog outputs as
well as receive a continuous stream of data from its data source. Because there is no
frame memory isolating the data streams, restrictions apply to the input frame timings.
Input and output processing of the encoder section are only coupled through the vertical
frequencies. In Master mode, the encoder provides a vertical sync and an odd/even pulse
to the input processing. In Slave mode, the encoder receives them.
The parameters of the input field are mainly given by the memory capacity of the encoder
section. The rule is that the scaler and thus the input processing needs to provide the
video data in the same time frames as the encoder reads them. Therefore, the vertical
active video times (and the vertical frequencies) need to be the same.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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