SAA7108AE Datasheet, PDF (115/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 73. Trigger control registers, subaddresses 6Ch and 6Dh, bit description
Legend: * = default value after reset.
Subaddress Bit Symbol
Access Value Description
6Ch
7 to 0 HTRIG[7:0] R/W 00h* sets the horizontal trigger phase related to
6Dh
7 to 5 HTRIG[10:8] R/W
0h* ^{chip-internal horizontal input[1]}
4 to 0 VTRIG[4:0] R/W
00h* sets the vertical trigger phase related to
chip-internal vertical input^[2]
[1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of
all internally generated timing signals.
[2] Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1Fh).
Table 74. Multi control register, subaddress 6Eh, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7
NVTRIG R/W
values of the VTRIG register are
0
positive
1
negative
6
BLCKON R/W 0* encoder in normal operation mode
1
output signal is forced to blanking level
5 and 4 PHRES[1:0] R/W
selects the phase reset mode of the color subcarrier
generator
00 no subcarrier reset
01 subcarrier reset every two lines
10 subcarrier reset every eight fields
11 subcarrier reset every four fields
3 and 2 LDEL[1:0] R/W
selects the delay on luminance path with reference to
chrominance path
00* no luminance delay
01 1 LLC luminance delay
10 2 LLC luminance delay
11 3 LLC luminance delay
1 and 0 FLC[1:0] R/W
field length control
00* interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at
60 Hz
01 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at
60 Hz
10 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at
60 Hz
11 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at
60 Hz
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
115 of 208