SAA7108AE Datasheet, PDF (110/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
SAA7108AE_SAA7109AE_3
Product data sheet
Table 62. Input port control 1 register, subaddress 3Ah, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7
CBENB R/W 0
data from input ports is encoded
1
color bar with fixed colors is encoded
6
-
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
5
SYNTV R/W
in Slave mode
0* the encoder is only synchronized at the beginning of an odd
field
1
the encoder receives a vertical sync signal
4
SYMP R/W
horizontal and vertical trigger
0* taken from FSVGC or both VSVGC and HSVGC
1
decoded out of ‘ITU-R BT.656’ compatible data at PD port
3
DEMOFF R/W
Y-C_B-C_R to RGB dematrix
0* active
1
bypassed
2
CSYNC R/W
pin HSM_CSYNC provides
0
horizontal sync for non-interlaced VGA components output
(at PIXCLK)
1
composite sync for interlaced components output (at XTAL
clock)
1
Y2C
R/W
input luminance data
0
twos complement from PD input port
1* straight binary from PD input port
0
UV2C R/W
input color difference data
0
twos complement from PD input port
1* straight binary from PD input port
Table 63. VPS enable, input control 2, subaddress 54h, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7
VPSEN R/W
video programming system data insertion
0* is disabled
1
in line 16 is enabled
6
-
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
5
GPVAL R/W
if GPEN = 1, pin VSM provides
0
LOW level
1
HIGH level
4
GPEN R/W
pin VSM provides
0* vertical sync for a monitor
1
constant signal according to GPVAL
3 and 2 -
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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