SAA7108AE Datasheet, PDF (146/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.2.15 Subaddress 0Eh
Table 156. Chrominance control 1; 0Eh[7:0]
Bit Description
Symbol Value
7
clear DTO
CDTO
0
1
6 to 4 color standard
selection
CSTD[2:0] 000
001
010
011
100
101
110
111
3
disable
DCVF
0
chrominance
vertical filter and
1
PAL phase error
correction
2
fast color time FCTC
0
constant
1
0
adaptive
CCOMB 0
chrominance
1
comb filter
Function
disabled
Every time CDTO is set, the internal subcarrier
DTO phase is reset to 0° and the RTCO output
generates a logic 0 at time slot 68 (see
document “How to use Real Time Control
(RTC)”, available on request). So an identical
subcarrier phase can be generated by an
external device (e.g. an encoder); if a DTO reset
is programmed via CDTO it has always to be
executed in the following order:
1. Set CDTO = 0
2. Set CDTO = 1
50 Hz/625 lines: PAL BGDHI (4.43 MHz)
60 Hz/525 lines: NTSC M (3.58 MHz)
50 Hz/625 lines: NTSC 4.43 (50 Hz)
60 Hz/525 lines: PAL 4.43 (60 Hz)
50 Hz/625 lines: combination-PAL N (3.58 MHz)
60 Hz/525 lines: NTSC 4.43 (60 Hz)
50 Hz/625 lines: NTSC N (3.58 MHz)
60 Hz/525 lines: PAL M (3.58 MHz)
50 Hz/625 lines: reserved
60 Hz/525 lines: NTSC-Japan (3.58 MHz)
50 Hz/625 lines: SECAM
60 Hz/525 lines: reserved
reserved; do not use
reserved; do not use
chrominance vertical filter and PAL phase error
correction on (during active video lines)
chrominance vertical filter and PAL phase error
correction permanently off
nominal time constant
fast time constant for special applications (high
quality input source, fast chroma lock required,
automatic standard detection off)
disabled
active
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
146 of 208