SAA7108AE Datasheet, PDF (170/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 219. Prescaler DC gain and FIR prefilter control; register set A [A2h[3:0]] and
B [D2h[3:0]]^[1] …continued
Prescaler DC gain
Control bits 3 to 0
XC2_1 XDCG2 XDCG1 XDCG0
Prescaler output is renormalized by gain
factor = ¹â„₁₂₈
X
1
1
1
Weighting of all accumulated samples is factor ‘1’; 0
X
X
X
e.g. XACL = 4 ⇒ sequence 1 + 1 + 1 + 1 + 1
Weighting of samples inside sequence is factor ‘2’; 1
X
X
X
e.g. XACL = 4 ⇒ sequence 1 + 2 + 2 + 2 + 1
[1] X = don’t care.
11.2.5.10 Subaddresses A4h to A6h
Table 220. Luminance brightness control; register set A [A4h[7:0]] and B [D4h[7:0]]
Luminance
brightness control
Control bits 7 to 0
BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0
Value = 0
0
0
0
0
0
0
0
0
Nominal value = 128 1
0
0
0
0
0
0
0
Value = 255
1
1
1
1
1
1
1
1
Table 221. Luminance contrast control; register set A [A5h[7:0]] and B [D5h[7:0]]
Luminance contrast Control bits 7 to 0
control
CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0
Gain = 0
0
0
0
0
0
0
0
0
Gain = ¹â„₆₄
0
0
0
0
0
0
0
1
Nominal gain = 64
0
1
0
0
0
0
0
0
Gain = ¹²⁷⁄₆₄
0
1
1
1
1
1
1
1
Table 222. Chrominance saturation control; register set A [A6h[7:0]] and B [D6h[7:0]]
Chrominance
saturation control
Control bits 7 to 0
SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0
Gain = 0
0
0
0
0
0
0
0
0
Gain = ¹â„₆₄
0
0
0
0
0
0
0
1
Nominal gain = 64
0
1
0
0
0
0
0
0
Gain = ¹²⁷⁄₆₄
0
1
1
1
1
1
1
1
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
170 of 208