SAA7108AE Datasheet, PDF (89/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 39. Audio clock pin description
Symbol Pin I/O Description
Bit
AMCLK K12 O audio master clock output ACPF[17:0] 32h[1:0] 31h[7:0] 30h[7:0] and
ACNI[21:0] 36h[5:0] 35h[7:0] 34h[7:0]
AMXCLK J12 I
external audio master clock -
input for the clock division
circuit, can be directly
connected to output
AMCLK for standard
applications
ASCLK
K14 O
serial audio clock output,
can be synchronized to
rising or falling edge of
AMXCLK
SDIV[5:0] 38h[5:0] and SCPH[3Ah[0]]
ALRCLK J13 O
audio channel (left/right)
clock output, can be
synchronized to rising or
falling edge of ASCLK
LRDIV[5:0] 39h[5:0] and LRPH[3Ah[1]]
10.3 Clock and real-time synchronization signals
For the generation of the line-locked video (pixel) clock LLC, and of the frame-locked
audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is
built-in for fundamental or third harmonic crystals. The supported crystal frequencies are
32.11 MHz or 24.576 MHz (defined during reset by strapping pin ALRCLK).
Alternatively pins XTALId and XTALIe can be driven from an external single-ended
oscillator.
The crystal oscillation can be propagated as a clock to other ICs in the system via
pin XTOUTd.
The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to
the selected video input, generating baseband video pixels according to “ITU
recommendation 601”. In order to support interfacing circuits, a direct pixel clock (LLC2) is
also provided.
The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various
real-time status information can be selected for the RTS pins. The signals are always
available (output) and reflect the synchronization operation of the decoder part in the
SAA7108AE; SAA7109AE. The function of the RTS1 and RTS0 pins can be defined by
bits RTSE1[3:0] 12h[7:4] and RTSE0[3:0] 12h[3:0]; see Table 40.
Table 40. Clock and real-time synchronization signals
Symbol Pin I/O Description
Crystal oscillator
XTALId P2 I input for crystal oscillator or reference clock
XTALOd P3 O output of crystal oscillator
XTOUTd P4 O reference (crystal) clock output drive (optional)
Real-time signals (RT port)
LLC
M14 O line-locked clock, nominal 27 MHz, double pixel
clock locked to the selected video input signal
Bit
-
-
XTOUTE[14h[3]]
-
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
89 of 208