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XC3S5000-5FGG676C Datasheet, PDF (99/272 Pages) Xilinx, Inc – Introduction and Ordering Information
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Spartan-3 FPGA Family: DC and Switching Characteristics
Configuration and JTAG Timing
X-Ref Target - Figure 36
VCCINT
(Supply)
1.0V
1.2V
VCCAUX
2.5V
(Supply)
2.0V
VCCO Bank 4
(Supply)
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Output)
1.0V
TPOR
TPROG
TPL
TICCK
DS099-3_03_120604
Notes:
1. The VCCINT, VCCAUX, and VCCO supplies may be applied in any order.
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 36: Waveforms for Power-On and the Beginning of Configuration
Table 65: Power-On Timing and the Beginning of Configuration
Symbol
TPOR(2)
TPROG
TPL(2)
TINIT
TICCK(3)
Description
Device
The time from the application of VCCINT, VCCAUX, and VCCO
Bank 4 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
The width of the low-going pulse on the PROG_B pin
All
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Minimum Low pulse width on INIT_B output
All
The time from the rising edge of the INIT_B pin to the
All
generation of the configuration clock signal at the CCLK
output pin
All Speed Grades
Min
Max
–
5
–
5
–
5
–
5
–
7
–
7
–
7
–
7
0.3
–
–
2
–
2
–
2
–
2
–
3
–
3
–
3
–
3
250
–
0.25
4.0
Units
ms
ms
ms
ms
ms
ms
ms
ms
μs
ms
ms
ms
ms
ms
ms
ms
ms
ns
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only for the Master Serial and Master Parallel modes.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
99
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