XC3S5000-5FGG676C Datasheet, PDF (153/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 94 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S50 in the PQ208
package. Similarly, Table 95 shows how the available user-I/O pins are distributed between the eight I/O banks for the
XC3S200 and XC3S400 in the PQ208 package.
Table 94: User I/Os Per Bank for XC3S50 in PQ208 Package
Package Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
15
9
0
2
2
Top
1
15
9
0
2
2
2
16
13
0
2
2
Right
3
16
12
0
2
2
4
15
3
6
2
2
Bottom
5
15
3
6
2
2
6
16
12
0
2
2
Left
7
16
12
0
2
2
GCLK
2
2
0
0
2
2
0
0
Table 95: User I/Os Per Bank for XC3S200 and XC3S400 in PQ208 Package
Package Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
16
9
0
2
3
Top
1
15
9
0
2
2
2
19
14
0
2
3
Right
3
20
15
0
2
3
4
17
4
6
2
3
Bottom
5
15
3
6
2
2
6
19
14
0
2
3
Left
7
20
15
0
2
3
GCLK
2
2
0
0
2
2
0
0
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
153