XC3S5000-5FGG676C Datasheet, PDF (23/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
upper path), enter the slice and connect directly to the LUT. Once inside the slice, the lower 4-bit path passes through a
function generator ‘F’ (or ‘G’) that performs logic operations. The function generator’s Data output, ‘D’, offers five possible
paths:
• Exit the slice via line ‘X’ (or ‘Y’) and return to interconnect.
• Inside the slice, ‘X’ (or ‘Y’) serves as an input to the DXMUX (DYMUX) which feeds the data input, ‘D’, of the FFX (FFY)
storage element. The ‘Q’ output of the storage element drives the line XQ (or YQ) which exits the slice.
• Control the CYMUXF (or CYMUXG) multiplexer on the carry chain.
• With the carry chain, serve as an input to the XORF (or XORG) exclusive-OR gate that performs arithmetic operations,
producing a result on ‘X’ (or ‘Y’).
• Drive the multiplexer F5MUX to implement logic functions wider than four bits. The ‘D’ outputs of both the F-LUT and
G-LUT serve as data inputs to this multiplexer.
In addition to the main logic paths described above, there are two bypass paths that enter the slice as BX and BY. Once
inside the FPGA, BX in the bottom half of the slice (or BY in the top half) can take any of several possible branches:
• Bypass both the LUT and the storage element, then exit the slice as BXOUT (or BYOUT) and return to interconnect.
• Bypass the LUT, then pass through a storage element via the D input before exiting as XQ (or YQ).
• Control the wide function multiplexer F5MUX (or F6MUX).
• Via multiplexers, serve as an input to the carry chain.
• Drives the DI input of the LUT.
• BY can control the REV inputs of both the FFY and FFX storage elements.
• Finally, the DIG_MUX multiplexer can switch BY onto the DIG line, which exits the slice.
Other slice signals shown in Figure 12 are discussed in the sections that follow.
DS099 (v3.1) June 27, 2013
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Product Specification
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