XC3S5000-5FGG676C Datasheet, PDF (13/272 Pages) Xilinx, Inc – Introduction and Ordering Information

X-Ref Target - Figure 8
Spartan-3 FPGA Family: Functional Description
DCM
180˚ 0˚
D1
Q1
CLK1
FDDR
DDR MUX
Q
D2
Q2
CLK2
DS099-2_02_070303
Figure 8: Clocking the DDR Register
Aside from high bandwidth data transfers, DDR can also be used to reproduce, or “mirror”, a clock signal on the output. This
approach is used to transmit clock and data signals together. A similar approach is used to reproduce a clock signal at
multiple outputs. The advantage for both approaches is that skew across the outputs will be minimal.
Some adjacent I/O blocks (IOBs) share common routing connecting the ICLK1, ICLK2, OTCLK1, and OTCLK2 clock inputs
of both IOBs. These IOB pairs are identified by their differential pair names IO_LxxN_# and IO_LxxP_#, where "xx" is an I/O
pair number and ‘#’ is an I/O bank number. Two adjacent IOBs containing DDR registers must share common clock inputs,
otherwise one or more of the clock signals will be unroutable.
Pull-Up and Pull-Down Resistors
The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os. The
pull-up resistor optionally connects each IOB pad to V_CCO. A pull-down resistor optionally connects each pad to GND. These
resistors are placed in a design using the PULLUP and PULLDOWN symbols in a schematic, respectively. They can also be
instantiated as components, set as constraints or passed as attributes in HDL code. These resistors can also be selected for
all unused I/O using the Bitstream Generator (BitGen) option UnusedPin. A Low logic level on HSWAP_EN activates the
pull-up resistors on all I/Os during configuration (see The I/Os During Power-On, Configuration, and User Mode, page 21).
The Spartan-3 FPGAs I/O pull-up and pull-down resistors are significantly stronger than the "weak" pull-up/pull-down
resistors used in previous Xilinx FPGA families. See Table 33, page 61 for equivalent resistor strengths.
Keeper Circuit
Each I/O has an optional keeper circuit that retains the last logic level on a line after all drivers have been turned off. This is
useful to keep bus lines from floating when all connected drivers are in a high-impedance state. This function is placed in a
design using the KEEPER symbol. Pull-up and pull-down resistors override the keeper circuit.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
13