XC3S5000-5FGG676C Datasheet, PDF (80/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 47: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
PCI33_3
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
Differential Standards
LDT_25 (ULVDS_25)
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
Add the Adjustment Below
Speed Grade
-5
-4
0.74
0.85
0.07
0.07
0.22
0.25
0.30
0.34
0.23
0.26
0.19
0.22
0.13
0.15
0.10
0.11
Units
ns
ns
ns
ns
ns
ns
ns
ns
–0.06
–0.09
0.02
–0.15
0.16
0.05
–0.02
0.75
0.13
0.10
–0.05
ns
–0.07
ns
0.04
ns
–0.13
ns
0.18
ns
0.06
ns
–0.01
ns
0.86
ns
0.15
ns
0.11
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth
in Table 32, Table 35, and Table 37.
2. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with
12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs
go into a high-impedance state.
3. For minimums, use the values reported by the Xilinx timing analyzer.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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