XC3S5000-5FGG676C Datasheet, PDF (53/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Configuration is automatically initiated after power-on unless it is delayed by the user. INIT_B is an open-drain line that the
FPGA holds Low during the clearing of the configuration memory. Extending the time that the pin is Low causes the
configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded.
The configuration process can also be initiated by asserting the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High. At this point, the configuration data is written to the FPGA. The FPGA pulses the
Global Set/Reset (GSR) signal at the end of configuration, resetting all flip-flops. The completion of the entire process is
signaled by the DONE pin going High.
X-Ref Target - Figure 31
Default Cycles
Start-Up Clock
Phase
0 1 2 3 4 5 67
DONE
GTS
GWE
Start-Up Clock
Phase
Sync-to-DONE
0 1 2 3 4 5 67
DONE
GTS
DONE High
GWE
DS099_028_060905
Figure 31: Default Start-Up Sequence
The default start-up sequence, shown in Figure 31, serves as a transition to the User mode. The default start-up sequence
is that one CCLK cycle after DONE goes High, the Global Three-State signal (GTS) is released. This permits device outputs
to which signals have been assigned to become active. One CCLK cycle later, the Global Write Enable (GWE) signal is
released. This permits the internal storage elements to begin changing state in response to the design logic and the user
clock.
The relative timing of configuration events can be changed via the BitGen options in the Xilinx development software. In
addition, the GTS and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the
devices to start synchronously. The sequence can also be paused at any stage, until lock has been achieved on any DCM.
Readback
Using Slave Parallel mode, configuration data from the FPGA can be read back. Readback is supported only in the Slave
Parallel and Boundary-Scan modes.
Along with the configuration data, it is possible to read back the contents of all registers, distributed RAM, and block RAM
resources. This capability is used for real-time debugging.
DS099 (v3.1) June 27, 2013
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Product Specification
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